Abstract: A memory control unit is coupled during use to a system bus for receiving memory addresses therefrom. The memory control unit is further coupled during use to one or more memory units by a second bus that includes a plurality of signal lines for transmitting, during a memory access cycle, a memory address to the one or more memory units. Each of the one or more memory units includes a plurality of semiconductor memory devices having a plurality of addressable memory storage locations. The memory control unit further includes circuitry that is responsive to a signal asserted by one of the memory units. The asserted signal indicates an access speed of the selected memory unit. The memory control unit specifies a duration of a memory access so as to make the duration of the memory access cycle compatible with the indicated access speed of at least the semiconductor memory devices of the selected memory unit.

Abstract: A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.

Abstract: A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.

Abstract: A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.

Abstract: A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.

Abstract: A memory control unit is coupled during use to a system bus for receiving memory addresses therefrom. The memory control unit is further coupled during use to one or more memory units by a second bus that includes a plurality of signal lines for transmitting, during a memory access cycle, a memory address to the one or more memory units. Each of the one or more memory units includes a plurality of semiconductor memory devices having a plurality of addressable memory storage locations. The memory control unit further includes circuitry that is coupled to and responsive to a signal asserted on the second bus by one of the memory units selected by the transmitted memory address. The asserted signal indicates an access speed of the selected memory unit, and specifies a duration of the memory access on an access-by-access basis so as to make a duration of the memory access cycle compatible with the access speed of at least the semiconductor memory devices of the selected memory unit.

Abstract: A memory control unit is coupled during use to a system bus for receiving memory addresses therefrom. The memory control unit is further coupled during use to one or more memory units by a second bus that includes a plurality of signal lines for transmitting, during a memory access cycle, a memory address to the one or more memory units. Each of the one or more memory units includes a plurality of semiconductor memory devices having a plurality of addressable memory storage locations. The memory control unit further includes circuitry that is coupled to and responsive to a signal asserted on the second bus by one of the memory units selected by the transmitted memory address. The asserted signal indicates an access speed of the selected memory unit, and specifies a duration of the memory access on an access-by-access basis so as to make a duration of the memory access cycle compatible with the access speed of at least the semiconductor memory devices of the selected memory unit.

Abstract: Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs.

Abstract: Disclosed are methods and apparatus for interfacing a central processor (12) (CP) and an IO controller (30) (IOC) to a main memory (40). A CP and an IO write buffer each include a pair of memory input data registers, located in a pair of Memory Data Unit (MDU) integrated circuits (38a, 38b), and also two memory address registers, a previous memory address register, and an address comparator, located in a Memory Address Unit (MAU) (36). These registers, in conjunction with associated control logic, are used to buffer CP and IO write addresses and data to the main memory. If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator. A match results in the combination of the previous write data and the current write data into one pending write, using write merge circuitry within the MDUs.

Abstract: A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.

Abstract: A method and apparatus for providing memory system status signals in an information processing system is disclosed. The memory system includes a bus which couples a memory unit, for storing information units, to a memory control unit. The memory control unit provides addresses to the memory unit. The memory unit stores or retrieves information units from memory locations corresponding to the provided address. The memory unit provides a status signal to the memory control unit indicating a status of the memory access being provided. The status signals provided by the memory unit indicate whether the provided memory address is within the range of addresses stored in the memory unit, the access speed of the memory devices in the memory unit, or the type of memory devices in the memory unit.

Abstract: A memory system connected by means of a system bus to other components of a data processing system. The memory system includes a memory control unit and at least one memory unit in which information units containing two words are stored. The memory control unit is connected to the system bus and receives system addresses and memory commands from the system bus, and depending on the memory command, receives data from or provides data to the system bus. A memory bus and lines for control signals specifying memory requests connect the memory control unit and the memory unit. The memory bus is time multiplexed between memory addresses and information units. The memory control unit receives a memory command, a system address, and in the case of a write command, system data on the system bus and produces the memory requests, memory addresses, and information units required to carry out the memory command.