Abstract: A peripheral device controller has an EEPROM which stores microinstructions to be placed in a random access memory control store. The EEPROM also stores peripheral configuration information. This information is obtained by polling the peripheral devices connected to the controller and storing the resulting information in the EEPROM. Upon powering up, the microinstructions stored in the EEPROM are transferred to the control store via execution of instructions held in a boot PROM. The controller, therefore, provides a fast control store while maintaining permanence of the microinstructions after power is extinguished. Means are also provided to update the control store and EEPROM. The EEPROM may upon CPU command be updated with new microinstructions held in main memory or obtained from peripheral devices.

Abstract: A plurality of units which are coupled to transfer requests, transfer data over an asynchronous bus network during allocated bus transfer cycles. The network has a tie-breaking bus priority network which is distributed to a common interface portion of each of the plurality of units and grants bus cycles and resolves simultaneous requests on a priority basis. At least one unit includes bus saturation detection apparatus included within its common interface portion for monitoring bus activity over established intervals of time. The detection of the occurrence of at least one available cycle over the given interval of time signals that the bus network is not in a saturated state. When the indicator specifies that the bus network is saturated, the unit throttles down its operation by increasing the amount of time between issuing data requests. Throttling continues until the bus is no longer being saturated.

Abstract: A controller connected between a system bus and peripheral devices has at least two microprocessors. One controls the data transfers with the peripheral devices, and the other controls data transfers with the system bus. The microprocessors share a data buffer and control store. This sharing is possible because of the controller timing means which synchronizes exclusive access to the shared components of the controller. When first initialized, the microprocessors are directed to execute a test instruction which points them to the beginning of their set of microinstructions. Once pointed to their set of microinstructions, normal operation may begin.

Abstract: Any host requesting acccess to the bus must, on its first attempt, wait for N arbitration delay periods after the bus becomes available before attempting to take control of the bus. If another host takes the bus before completion of the arbitration delay period, the host must wait till the next time the bus becomes available. The arbitration delay count is decreased by one for each successive attempt, until the host either gains control of the bus or the aribration delay period goes to zero. At this point it may attempt to take control of the bus as soon as the bus becomes available. If another higher priority host reaches an arbitration delay count of zero during the same arbitration delay count period, the host will be denied and will wait for the next time the bus becomes available, again with an arbitration delay count of zero.

Abstract: A controller controls data transfers between a data processing system bus and peripheral devices. In the controller, data buffers are divided into page frames. Paging circuitry provides for allocation and deallocation of pages to and from the data buffer. Included in the page circuitry is a paging RAM. The paging RAM and other paging circuitry components allow contiguously addressed pages of data to be stored in noncontiguous locations in the data buffer. There may be more than one data buffer and these data buffers may be exclusively seized by microprocessors in the controller via seizing logic.

Abstract: A disk controller address register is used to address both a disk controller memory and a system memory between which data is transferred as it is stored on or retrieved from a disk storage device. A single address is provided to the address register which then develops other addresses needed in the data transfer between the two memories.

Abstract: Information read from a disk device includes synchronization bytes to enable a controller to get into byte synchronization with a stream of bits received from the disk. The stream of bits passes through a shift register. Firmware conditions a multiplexer which receives the parallel output of the serial register to select the high order binary ONE bit thereby enabling the controller to get into byte synchronization with the stream of bits.

Abstract: In a peripheral controller of a data processing system having a plurality of system units electrically coupled to a common communication bus for asynchronous intercommunication, an array of counters responsive to both hardware and firmware are connected in a manner to form a serial control data path. Prior to a data transfer, a serial data stream including an offset range count, a range count and a main memory address is shifted through the counters under firmware control. During a data transfer, the firmware enables the hardware control to increment the memory address and decrement the range count to accommodate the higher data transfer rates characteristic of hardware control.

Abstract: In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the absence of data in its input register and the presence of data in its output register. The signals are logically combined and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states. During such transfer states, data is transferred under hardware control between the FIFO buffer and main memory.

Abstract: A firmware/hardware method and system is provided for testing interface logic in a data processing system having a plurality of system units intercommunicating over a common electrical bus. Under firmware control, an incorrect parity is generated in a main memory address to be loaded into output registers of a system unit supplying information to the bus. A bus cycle request is issued by the system unit, and when the bus is made available the system unit acknowledges the memory address to initiate a transfer of data from the bus into the input registers of the system unit. Thereafter, the data in the output registers of the device may be compared with the data in the input registers to detect interface logic errors.

Abstract: A logic data control system including a first-in-first-out (FIFO) buffer predictor is provided for the transfer of data between a main memory unit and a peripheral control unit of a data processing system. Data from main memory is stored into the input registers of the peripheral unit, and thereafter loaded into an array of data FIFOs for transfer to a peripheral storage device. A predictor FIFO operates in parallel with the data FIFOs, and is loaded with a dummy or flag byte each time a data request is made to main memory. When a data word is loaded into the data FIFOs, the input register of the predictor FIFO is sensed. If the flag byte in the predictor FIFO has dropped from the input register into the FIFO stack, a request is issued to main memory for an additional data word. When the data FIFOs are filled, the predictor FIFO also is filled and cannot generate an additional data request until a data byte has been unloaded from the data FIFOs to a peripheral storage device.