Abstract: A memory system having a read/write head is provided wherein a system clock or a test clock can be used to initiate a pulse for enabling the read/write head during a write period and a delay circuit coupled to the system clock or to the test clock can be used to terminate the enabling or control pulse, with a write clock having an input coupled to the system clock also used to terminate the enabling or control pulse during a write period.

Abstract: A memory system is provided wherein array signals begin at the start of a first phase of a system clock and a sense amplifier set signal is developed during a second phase of the system clock which includes an array of memory cells including word lines and bit lines, word drivers connected to the word lines, a word address decoder enabled by the first phase of the clock system and coupled to the word drivers, a bit switch coupling a bit line to a sense amplifier, a system clock inverting circuit, a timing circuit having a first input connected to a late select signal, a second input connected to the inverting circuit and an output connected to the bit switch and a delay circuit having an input coupled to the inverting circuit and an output connected to the sense amplifier.