Abstract: An input/output processing system includes an input/output processing unit and a read only memory (ROM) and a read/write memory. The ROM is coded to include instructions of a number of control routines. The read/write memory includes locations for storing instructions and data. The processing unit includes a plurality of registers for storing information used in developing addresses for accessing each memory. It further includes a control register for storing information for controlling accesses to the memories and a steering register which operatively couples to the control register and stores information designating which one of the memories is to be accessed. The processing unit is conditioned to exclusively OR the information in the control register with the information contained in one of the plurality of registers.

Abstract: An input/output system includes at least a pair of processing units and system interface apparatus for comparing the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus includes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the processing units is faulty. The system interface apparatus, following signal indications of a certain minimum confidence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables system operation to be continued with the good processing unit.