Abstract: A first subset of semiconductor devices has an associated first additional device and a first gate output. A second subset of semiconductor devices has an associated second additional device and a second gate output. The first and second subsets are of one conductivity type while the first and second additional devices are of another conductivity type. First logic signals are applied to the first subset for turning on the first subset and the first additional device for producing at the first gate output a first function of the first logic signals. Second logic signals are applied to the second subset for turning on the second subset and the second additional device for producing at the second gate output a second function of the second logic signals.

Abstract: A solid state timepiece having a chain of series connected counters with clock pulses being applied to the first counter in the chain. A reset system is responsive to reset signals and is coupled to the counters for selective resetting of the counters upon application of predetermined reset signals. A decoder system independent of the resetting of the counters detects the state of the reset signals during a predetermined time duration and produces a control signal upon application of selected reset signal states. A control system provides internal control of the timepiece only upon application of the control signal.