Abstract: A method and system for determining an initial architectural state for instruction trace reconstruction. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well-known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace. However, the initial architectural state (the state of all caches, buffers and registers) must be determined in order to accurately reconstruct an instruction trace. At least one cache within the processor system is divided into two portions, the content of that cache is invalidated and each cache entry thereafter is duplicated within each portion of the divided cache.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine address traces, data addresses and data during the trace, if the initial architectural state is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained.

Abstract: A method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyzes and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace, if the initial architectural state of the system is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained.

Abstract: A method and system for performing performance monitoring within a data processing system whereby a counting function to be performed by a particular counter within the performance monitor is dependent upon a particular event programmed within another counter within the performance monitor so that reprogramming of all code points for each performance counter is not required.

Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Abstract: The present invention provides a system and method which ensures that machine state data, for each CPU in an MP system, corresponding to a specific point in time will always be saved, regardless of whether the system interrupt handler is enabled or disabled. A series of special purpose registers (SPR) are included, which are associated with the performance monitoring mechanism in each processor in the MP system. A time base mechanism in each CPU is used and synchronized across the entire MP system. When the time base mechanism requests that the machine state be recorded, the performance monitor then immediately stores the machine state values in the special purpose registers. Thus, the state of the each CPU in the MP system is saved at the identical point in time. The performance monitor issues an interrupt request to the interrupt handler and, if interrupts are enabled, the machine state data is stored for post-processing, or the like.

Abstract: A method and system for identifying inhibited interrupts in a processor system, the processor system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes initializing the at least one PMC and counting a number of cycles or occurrences with the at least one PMC that exceptions are ignored during a predetermined sampling period. In a second aspect the method and system provides for initializing at least one PMC and counting a number of cycles or occurrences with the at least one PMC that an interrupt is pending during the predetermined sampling period. The counted number of cycles/occurrences assists in identifying potential areas of improving system performance in order to reduce the counted values.

Abstract: A method for identifying bottlenecks within a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PMCs, includes, for a predetermined sampling period, counting a number of cycles that a dispatch unit is stalled, counting a number of cycles that each of a plurality of execution units is stalled, counting a number of cycles that a load/store unit is stalled, and counting a number of cycles that a completion unit is stalled. The counting in the units is performed to identify the relative effect of stalls occurring within each unit during processing to produce an overview of relative effect of the stalling of each unit on the total system bottleneck conditions.

Abstract: A method and system for reconstructing a relationship among events in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes controlling a mode of updating the at least one PMC through a bit set within the at least one MMCR, the bit set having a plurality of logic levels. Further included are determining if the bit set is at a first logic level, and placing the at least one PMC in a history mode if the bit set is at the first logic level.

Abstract: A method and system for monitoring performance of a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PMCs, includes identifying misaligned data items, and determining a performance penalty of misaligned data accesses during a predetermined sampling period.

Abstract: A method and system for determining the effectiveness of operation of a branch of a branch unit in a processing system the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one of the PMC, includes accumulating count data during branch unit operation with the at least one during a predetermined sampling period, and determining effectiveness of branch prediction based on the accumulated count data.

Abstract: A thresholding mechanism and method for performance monitoring of memory array access distribution times is disclosed. A data request signal sent to the memory hierarchy activates a first counter, having a first count value. A clock coupled to the first counter increments the first count value with each clock cycle, while also decrementing a decrementer having a predetermined threshold value. The first counter is deactivated by a completion signal when the data request is completed. A second counter having a second count value is incremented when the first count value is greater than the threshold value by the time the data request is complete.

Abstract: A method and system for determining the efficiency of operation of a dispatch unit in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes counting a number of instructions dispatched by the dispatch unit during a predetermined sampling period, counting a number of times a predetermined number of instructions are dispatched by the dispatch unit per cycle during the predetermined sampling period, and determining the efficiency of the dispatch unit according to the counted number of instructions and the counted number of times the predetermined number of instructions are dispatched by the dispatch unit.