Abstract: An apparatus and method are disclosed that provide system time base generation in a data processing system. The data processing system may have a single microprocessor or have multiple microprocessors. In either case, the data processing system has a plurality of devices that are time dependent upon the lead microprocessor within the data processing system. The apparatus includes a system clock generation circuit coupled to the microprocessor via a bus interface and a clock prescalar, further coupled to the system clock generation circuit and the bus interface, that is used to provide a clock pulse adjustment based upon a threshold count level as determined by the system clock generation circuit and the microprocessor.

Abstract: A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bus to bus bridge connects between a primary bus and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. Each bus to bus bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information.

Abstract: A method for managing a data transfer between a first device and an allocated portion of common memory including the steps of receiving a reallocation request of the allocated portion of common memory from a second device, receiving a veto of the requested reallocation from the first device, and delaying the reallocation request. In addition, a method for transferring data between a peripheral device and a common memory in a virtual memory system including the steps of instructing the peripheral device to transfer data with an allocated portion of the common memory, requesting a reallocation of the allocated portion of the common memory, and receiving a veto of the requested reallocation from the peripheral device in response to the instructed data transfer.