Abstract: CODECs and various other types of communication devices require timing information to enable them to transmit and receive digital information at the proper time. In the case of multiple CODECs on a single integrated circuit, this has typically required devoting terminals to provide separate transmit and receive frame synchronization pulses for each CODEC. Alternatively, a microprocessor interface may be included so that internal registers can be loaded with transmit and receive timing information. However, that approach limits timing flexibility. In the present invention, a "frame synchronization separation pulse" (FSEP) provides the separation in time between transmit and receive synchronization pulses. In this manner, the number of integrated circuit terminals required for synchronization may be reduced.

Abstract: An automatic gain control (AGC) amplifier circuit uses a control loop comprising a digital counter (70) which controls a multiplying digital-to-analog converter (10) arranged as an attenuator of the input v to the AGC. The counter (70) is arranged to count up or down depending upon the output signal of the AGC circuit. In addition, a latency can be introduced into the control loop so that in case of most signal envelope variations, the counter is frozen to prevent output fluctuations.

Abstract: Current source circuitry consisting of a first n-channel field effect transistor (FET) and voltage generator circuitry coupled to the gate of the first FET. The voltage generator circuitry acts to control the current through the first FET such that it is essentially constant even with power supply, temperature, and many processing variations. The voltage generator circuitry consists of a second FET, a two input differential operational amplifier, a resistor, and an n-p-n transistor if the resistor has a positive temperature coefficient. A negative feedback path using the amplifier and the second FET ensures against current changes in the first and second FETs even if there are changes in one of the power supply levels and/or many semiconductor processing variations.

Abstract: The source-drain resistance of an MOS load transistor (M.sub.2) is linearized by means of a pair of properly designed auxiliary MOS transistors (M.sub.3 and M.sub.4) whose source-drain paths are electrically coupled (conductively or through an amplifier) with the load transistor (M.sub.2). The gate electrode of the load transistor (M.sub.2) is connected to the common node point (N.sub.34) between the auxiliary transistors (M.sub.3 and M.sub.4); whereas the transconductances (.beta..sub.3 and .beta..sub.4) of the auxiliary transistors (M.sub.3 and M.sub.4) are designed such that during operation the resulting feedback signal from the common node point (N.sub.34) to the gate electrode of the load transistor (M.sub.2) reduces its nonlinearity.