Abstract: An improved network architecture for minimizing latency of preparing and sending data to a network over a physical medium. A system for communicating messages over a network may create and store ready-to-send data packets in a data buffer next to or as close as possible, either physically and/or logically, to a MAC component. The MAC component may then receive the data packet directly from the data buffer and encapsulate the data packet into a frame suitable for transmission to the network. The data packet is modifiable while being stored in the data buffer prior to transmission to the network.

Abstract: An improved network architecture for minimizing latency of preparing and sending data to a network over a physical medium. A system for communicating messages over a network may create and store ready-to-send data packets in a data buffer next to or as close as possible, either physically and/or logically, to a MAC component. The MAC component may then receive the data packet directly from the data buffer and encapsulate the data packet into a frame suitable for transmission to the network. The data packet is modifiable while being stored in the data buffer prior to transmission to the network.

Abstract: A data processing system comprises a first clock domain having a first clock rate, a second clock domain having a second clock rate, and a data path operable to transfer data items from the first clock domain to the second clock domain. The data path comprises a buffer having an input for receiving data items from the first clock domain, and an output port for transmitting data items to the second clock domain in a first-in first-out manner. The buffer has a first pointer for indication of a current first location of the buffer, and a second pointer for indication of a current second location of the buffer. The system further includes a read controller operable to define a read pattern for the buffer, to control output from the buffer in dependence upon such a read pattern, and to adjust such a read pattern in dependence upon a value of such a first pointer for the buffer.

Abstract: The present invention provides a multi-path network for use in a bridge, switch, router, hub or the like, comprising a plurality of network ports adapted for connection with one or more devices, each device having a different identifying address data; a plurality of network elements; and a plurality of network links interconnecting the network elements and connecting the network elements to the network ports, wherein the multi-path network further comprises separately addressable memory elements each adapted for storing device address data and the multi-path network is adapted to distribute a plurality of device address data amongst the plurality of memory elements.

Abstract: The present invention provides a method of limiting the frequency of floods within a data network, the floods arising as a data frame is routed to an unknown destination, the method comprising the steps of: receiving on an ingress port a data frame intended for a destination station and containing a MAC address of that station; checking the destination MAC address with the contents of a MAC table; and thereby determining whether the data frame is to be routed, discarded or flooded to all ports except the ingress port; and respectively routing, discarding or flooding the data frame to all ports except the ingress port.

Abstract: A data processing system comprises a first clock domain having a first clock rate, a second clock domain having a second clock rate, and a data path operable to transfer data items from the first clock domain to the second clock domain. The data path comprises a buffer having an input for receiving data items from the first clock domain, and an output port for transmitting data items to the second clock domain in a first-in first-out manner. The buffer has a first pointer for indication of a current first location of the buffer, and a second pointer for indication of a current second location of the buffer. The system further includes a read controller operable to define a read pattern for the buffer, to control output from the buffer in dependence upon such a read pattern, and to adjust such a read pattern in dependence upon a value of such a first pointer for the buffer.

Abstract: The present invention provides a method of limiting the frequency of floods within a data network, the floods arising as a data frame is routed to an unknown destination, the method comprising the steps of: (a) receiving (42) on an ingress port a data frame intended for a destination station and containing a MAC address of that station; (b) checking (50) the destination MAC address with the contents of a MAC table; and thereby (c) determining (50, 54, 58, 62) whether the data frame is to be routed (56), discarded (60, 66) or flooded (52, 64) to all ports except the ingress port; and (d) respectively routing (56), discarding (60, 66) or flooding (52, 64) the data frame to all ports except the ingress port, as determined in Step (c).

Abstract: The present invention provides a multi-path network for use in a bridge, switch, router, hub or the like, comprising a plurality of network ports adapted for connection with one or more devices, each device having a different identifying address data; a plurality of network elements; and a plurality of network links interconnecting the network elements and connecting the network elements to the network ports, wherein the multi-path network further comprises separately addressable memory elements each adapted for storing device address data and the multi-path network is adapted to distribute a plurality of device address data amongst the plurality of memory elements.

Abstract: A receiver for high-speed serial communication that uses an interface such as XAUI is disclosed with automatic lane assignment. The receiver analyzes incoming data packets and determines the lanes based on the data packets. The lanes are then automatically reordered. The receiver allows the lanes to be connected to the receiver arbitrarily, thereby providing additional layout freedom to circuit board and ASIC designers.