Patents by Inventor Edward M. DeMulder

Edward M. DeMulder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and structure for optimizing yield of 3-D chip manufacture
    Patent number: 7999377
    Abstract: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Edward M. DeMulder, Sarah H. Knickerbocker, Michael J. Shapiro, Albert M. Young
  • Method and structure for optimizing yield of 3-D chip manufacture
    Patent number: 7737003
    Abstract: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Edward M. DeMulder, Sarah H. Knickerbocker, Michael J. Shapiro, Albert M. Young
  • Method and Structure for Optimizing Yield of 3-D Chip Manufacture
    Publication number: 20080142959
    Abstract: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.
    Type: Application
    Filed: February 11, 2008
    Publication date: June 19, 2008
    Inventors: Edward M. DeMulder, Sarah H. Knickerbocker, Michael J. Shapiro, Albert M. Young