Abstract: Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1.

Abstract: Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1.

Abstract: A method for measuring the proper exposure and registration of layers of desired circuit features on an integrated circuit wafer. The process of making the integrated circuit feature is modified in three ways. First, a structure is added to the mask pattern for each layer, apart from the desired circuit feature and parallel with and abutting the previous layer structure, comprising a plurality of geometric patterns arranged in a progressively overlapping edge-to-edge orientation on the mask pattern. The progressive overlap is such that at one end of the structure there is a substantial separation between the opposing edges of the geometric patterns, in the middle of the structure the opposing edges of the geometric patterns meet, and at the other end of the structure there is a substantial overlap of the opposing edges of the geometric patterns. The non-opposing edges of the geometric patterns are offset relative to a reference pattern in the middle of the structure.