Patents by Inventor Edward P. Maciejewski
Edward P. Maciejewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8456169Abstract: A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.Type: GrantFiled: January 13, 2010Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Qingqing Liang, Edward P. Maciejewski
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Patent number: 8354309Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.Type: GrantFiled: January 10, 2012Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski, Myung-Hee Na, Edward J. Nowak, Xiaojun Yu
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Publication number: 20120187529Abstract: An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.Type: ApplicationFiled: January 25, 2011Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: Edward P. Maciejewski, Dustin Kenneth Slisher, Stefan Zollner
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Publication number: 20120168874Abstract: Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.Type: ApplicationFiled: March 1, 2012Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Sunfei Fang, Brian J. Greene, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang
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Publication number: 20120119294Abstract: A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicant: International Business Machines CorporationInventors: BRIAN J. GREENE, Jeffrey B. Johnson, Qingqing Liang, Edward P. Maciejewski
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Patent number: 8173531Abstract: A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.Type: GrantFiled: August 4, 2009Date of Patent: May 8, 2012Assignee: International Business Machines CorporationInventors: Sunfei Fang, Brian J. Greene, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang
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Publication number: 20120108017Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.Type: ApplicationFiled: January 10, 2012Publication date: May 3, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski, Myung-Hee Na, Edward J. Nowak, Xiaojun Yu
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Patent number: 8106455Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.Type: GrantFiled: April 30, 2009Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski, Myung-Hee Na, Edward J. Nowak, Xiaojun Yu
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Publication number: 20110169499Abstract: A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.Type: ApplicationFiled: January 13, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manjul Bhushan, Mark B. Ketchen, Qingqing Liang, Edward P. Maciejewski
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Publication number: 20110031554Abstract: A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.Type: ApplicationFiled: August 4, 2009Publication date: February 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sunfei Fang, Brian J. Greene, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang
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Publication number: 20100276753Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.Type: ApplicationFiled: April 30, 2009Publication date: November 4, 2010Applicant: International Business Machines CorporationInventors: Brian J. Greene, Michael P. Chudzik, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski, Myung-Hee Na, Edward J. Nowak, Xiaojun Yu
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Patent number: 7583125Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.Type: GrantFiled: October 25, 2007Date of Patent: September 1, 2009Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Chandrasekharan Kothandaraman, Edward P. Maciejewski
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Patent number: 7504875Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.Type: GrantFiled: October 25, 2007Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Chandrasekharan Kothandaraman, Edward P. Maciejewski
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Patent number: 7408421Abstract: A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including a non-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the non-silicided poly-silicon resistor. The dimensions of the non-silicided poly-silicon resistor are large enough so that the resistance of the non-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the non-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.Type: GrantFiled: July 5, 2006Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, Edward P. Maciejewski, Noah D. Zamdmer
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Patent number: 7396694Abstract: Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.Type: GrantFiled: October 6, 2006Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Ishtiaq Ahsan, Edward P. Maciejewski
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Patent number: 7354805Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.Type: GrantFiled: April 25, 2007Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: Chandrasekharan Kothandaraman, Edward P. Maciejewski
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Publication number: 20080007354Abstract: A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including an un-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the un-silicided poly-silicon resistor. The dimensions of the un-silicided poly-silicon resistor are large enough so that the resistance of the un-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the un-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.Type: ApplicationFiled: July 5, 2006Publication date: January 10, 2008Inventors: Ishtiaq Ahsan, Edward P. Maciejewski, Noah D. Zamdmer
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Patent number: 7295057Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.Type: GrantFiled: January 18, 2005Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Chandrasekharan Kothandaraman, Edward P. Maciejewski
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Patent number: 7242072Abstract: A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.Type: GrantFiled: November 23, 2004Date of Patent: July 10, 2007Assignee: International Business Machines CorporationInventors: Chandrasekharan Kothandaraman, Edward P. Maciejewski
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Patent number: 7227204Abstract: A device is provided which includes a single-crystal semiconductor region disposed in a substrate. The single-crystal region includes a first semiconductor material and a diode disposed in the single-crystal region. The diode includes an anode region including a first alloy region, being an alloy of the first semiconductor material with a second semiconductor material, and a second region which consists essentially of the first semiconductor material, the diode further including a cathode region.Type: GrantFiled: February 16, 2005Date of Patent: June 5, 2007Assignee: International Business Machines CorporationInventors: Edward P. Maciejewski, Sherry A. Womack, Shreesh Narasimha, Christopher D. Sheraw