Patents by Inventor Edward R. Vokoun

Edward R. Vokoun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5943591
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: August 24, 1999
    Assignee: VLSI Technology
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5795815
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: August 18, 1998
    Assignee: VLSI Technology, Inc.
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5686171
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: November 11, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5392113
    Abstract: Method and apparatus for detecting the presence of selected types of defects, such as chemical stains from a liquid photoresist material or a liquid dielectric material, on a non-visible chosen surface of a semiconductor water that has undergone at least one processing step. In one embodiment, a support substrate for, the wafer is provided that has a highly reflecting surface adjacent to the chosen surface. The reflecting surface and the chosen surface are moved apart, and the chosen surface is illuminated with light to form an optical image of the chosen surface. The optical image of the chosen surface is reflected in the reflecting surface, and the reflected optical image is examined for the presence of selected types of defects. In another embodiment, a portion of this reflecting surface is initially contiguous to the chosen surface.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: February 21, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Anthony Sayka, Stacy W. Hall, Judy U. Galloway, Pierre Leroux, Bryan D. Schmidt, Daniel D. Siems, Henry B. Taylor, III, Edward R. Vokoun
  • Patent number: 5296893
    Abstract: A reticle box characterized by a generally rectangular base member having a base portion and four contiguous wall portions, a generally rectangular cover member which can be engaged with the base member to fully enclose a reticle, and a closing mechanism which causes resilient stand-offs attached to the base member and the cover member to firmly grip the reticle within the box. Mating peripheral seals are provided around portions of the base member and the cover member to prevent the influx of contaminants. The cover member is of unitary design with an integral frame portion, central cover portion, and hinge. The reticle box is preferably made from a non-static plastic material.
    Type: Grant
    Filed: July 31, 1992
    Date of Patent: March 22, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: Charles G. Shaw, Edward R. Vokoun, III
  • Patent number: 5096855
    Abstract: A method (and semiconductor devices and wafers producers therefrom) is provided which method comprises providing a semiconductor wafer which comprises at least two physically interconnected semiconductor devices including at least one scribe lane formed at a peripheral edge between the semiconductor devices; covering at least a portion of the scribe lane with a continuous metal film, forming metal limiting means in the metal film of predetermined configuration and spacing so that no space between the metal limiting means exceeds 10 microns in any direction; and thereafter scribing the semiconductor wafer to produce a device containing bent metal portions within the range of 0 to 10 microns.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: March 17, 1992
    Assignee: U.S. Philips Corporation
    Inventor: Edward R. Vokoun, III
  • Patent number: 5003374
    Abstract: A method and semiconductor devices and wafers produced therefrom are provided which comprise at least one scribe lane formed in at least a peripheral edge, a metal film covering at least a portion of said scribe lane and having metal limiting means so preselectively spaced and configured that scribing the wafer in any direction along said portion of the scribe lane containing metal limiting means will result in a bent metal portion within the range of about 0 to 10 microns.
    Type: Grant
    Filed: May 23, 1988
    Date of Patent: March 26, 1991
    Assignee: North American Philips Corporation
    Inventor: Edward R. Vokoun, III