Abstract: In one embodiment, an apparatus includes a storage presentation module and a mapping module in communication with the storage presentation module and an object pool module. The storage presentation module is operable to provide a first storage interface and a second storage interface via a network interface. The first storage interface is associated with a first storage resource accessible via a first storage protocol, and the second storage interface is associated with a second storage resource accessible via a second storage protocol different from the first storage protocol. The mapping module is operable to receive from the storage presentation module a request for access to the first storage resource based on the first storage protocol and a request for access to the second storage resource based on the second storage protocol.

Abstract: The SCSI control block interface provides for distributed processing of storage commands that provides transports and processing blocks the ability to interconnect with each other independent of the underlying transport or hardware architecture. The interface receives a SCSI control block from a transport and determines a storage command associated with the SCSI control block. Based upon the storage command, a particular processor that processes the storage command is determined. The SCSI control block is routed to the appropriate processor for processing. After processing, the SCB is routed to a transport for delivery.

Abstract: The SCSI control block interface provides for distributed processing of storage commands that provides transports and processing blocks the ability to interconnect with each other independent of the underlying transport or hardware architecture. The interface receives a SCSI control block from a transport and determines a storage command associated with the SCSI control block. Based upon the storage command, a particular processor that processes the storage command is determined. The SCSI control block is routed to the appropriate processor for processing. After processing, the SCB is routed to a transport for delivery.

Abstract: A method of communicating between first and second controllers (including between processes within the controllers, or microprocessors) on an I2C bus is provided. The I2C bus is of the type which transmits data packets that start with a start condition and end with a stop condition, and that includes a destination address followed by a transmission type, a first data byte, a second data byte, and one or more additional data bytes. The method includes the steps of: designating a destination address with a unique bus address (i.e., devAddress) of the second controller; designating the first data byte with a unique bus address (i.e., ownAddress) of the first controller; and specifying the transmission type, wherein the first and second controllers initiate a master-slave relationship for read and write operations between controllers. The invention also provides an I2C bus protocol system. The system includes an I2C bus with means for communicating an I2C packet across the bus.

Abstract: The invention includes a method for transferring user data between a first data communications device and a second data communications device over a data link. The first data communications device transmits a DLE-BEL to the second data communications device to request initialization. The second data communications device transmits a DLE-SI to the first data communications device in response to the DLE-BEL to indicate initialization to receive the user data. The first data communications device transmits a DLE-STX to the second data communications device in response to the DLE-SI to identify the start of a frame of user data. The first data communications device transmits at least a portion of the user data to the second data communications device after transmitting the DLE-STX. The first data communications device transmits a frame-ending control code to the second data communications device after transmitting the user data. The frame-ending control code is either a DLE-ETB, DLE-ETX, or DLE-ESC.

Abstract: A host computer having a CPU and a FIFO memory connected to an I/O adapter for the exchange of I/O information between the host and the adapter. The host writes I/O commands and stores them in a relatively small FIFO memory of the host. The I/O commands are then copied to a relatively large I/O memory array in the I/O adapter where they are stored until the I/O command is completed. The FIFO is then free for use by other I/O commands from the host CPU. I/O completion information is returned to a completion queue in the host by the adapter. This information includes completion status and an indication of the number of I/O commands copied to the adapter from the host FIFO. This allows the CPU to invalidate and reuse all FIFO locations containing I/O commands that have been copied from the FIFO to the adapter I/O array.