Abstract: Various embodiments associated an inter-network policy that is implemented for use across multiple networks are described. Individual networks can have individual policies that govern how communications are handled, how resources are allocated, and other metrics. When individual networks work together, these networks can experience problems if their individual policies conflict with one another. Therefore, the inter-network policy can be generated that facilitates the individual networks working together.

Abstract: Various embodiments associated an inter-network policy that is implemented for use across multiple networks are described. Individual networks can have individual policies that govern how communications are handled, how resources are allocated, and other metrics. When individual networks work together, these networks can experience problems if their individual policies conflict with one another. Therefore, the inter-network policy can be generated that facilitates the individual networks working together.

Abstract: An electronic circuit is used to compare two sequences, such as genetic sequences, to determine which alignment of the sequences produces the greatest similarity. The circuit includes a linear array of series-connected processors, each of which stores a single element from one of the sequences and compares that element with each successive element in the other sequence. For each comparison, the processor generates a scoring parameter that indicates which segment ending at those two elements produces the greatest degree of similarity between the sequences. The processor uses the scoring parameter to generate a similar scoring parameter for a comparison between the stored element and the next successive element from the other sequence. The processor also delivers the scoring parameter to the next processor in the array for use in generating a similar scoring parameter for another pair of elements.

Abstract: A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767.

Abstract: In a multi-node network containing a plurality of parallel and distributed nodes, this invention reduces the time to establish a through-path or make a decision that no through-path can be established at the present time. In one aspect, each node that can be an originating node contains connectivity analysis logic which performs a minimum cycle breakdown of the possible paths between the originating node and the destination node to establish a list of nodes to be tried before attempting to establish a through-path to a destination node whereby exhaustive testing of all paths is not undertaken. In another, each node that can be an intermediate node contains pruning logic for pruning a non-variable tested path and all associated paths depending therefrom from further testing whereby redundant testing of paths which will result in failure is eliminated.

Abstract: The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.