Patents by Inventor Edward Tyburski

Edward Tyburski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Relative synchronization system for a telephone network
    Patent number: 5500853
    Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization, and also provides alarm correlation and hierarchical event filtering.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: March 19, 1996
    Assignee: Applied Digital Access, Inc.
    Inventors: Thomas L. Engdahl, Edward Tyburski, Paul R. Hartmann
  • Alarm correlation system for a telephone network
    Patent number: 5495470
    Abstract: A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization, and also provides alarm correlation and hierarchical event filtering.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: February 27, 1996
    Assignee: Applied Digital Access, Inc.
    Inventors: Edward Tyburski, Paul R. Hartmann