Abstract: Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory with new user data. Re-encoding ECC comprises comparing new ECC with the most recent ECC of the previous syndrome, correcting a bit error in the new ECC, and indicating if the new ECC has failed.

Abstract: Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory with new user data. Re-encoding ECC comprises comparing new ECC with the most recent ECC of the previous syndrome, correcting a bit error in the new ECC, and indicating if the new ECC has failed.

Abstract: Methods and apparatus are disclosed for erasing a core memory cell using a negative gate voltage in a semiconductor memory device, wherein negative pump MOS regulation capacitors are pre-charged according to a pre-charge signal during a core cell erase operation. A negative voltage pump is then regulated using the pre-charged negative pump MOS regulation capacitors to provide the negative gate voltage. Apparatus is disclosed for pre-charging negative pump MOS regulation capacitors during a core cell erase operation in a memory device, which comprises a switch connected between a reference voltage and the negative pump MOS regulation capacitors, and a pre-charge control circuit providing a pre-charge signal to the switch to selectively connect the reference voltage to the negative pump MOS regulation capacitors for pre-charging thereof in an erase operation.

Abstract: In a method and system for diagnosing a back-end state machine used for testing flash memory cells fabricated on a semiconductor substrate, a signal selector and a diagnostic matching logic are fabricated on the semiconductor substrate. The diagnostic matching logic sets a generated match output to a pass or fail state depending on control variables from the back-end state machine. The signal selector selects the generated match output to be used in a verify step of a BIST (built-in-self-test) mode, if a diagnostic mode is invoked. The back-end state machine performs a plurality of BIST modes with the generated match output, for testing the functionality of the back-end state machine.

Abstract: An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.

Abstract: A memory device and a method for compensating for a load current in the memory device. The memory device includes a plurality of I/O buffers where each I/O buffer includes an I/O write-buffer driver circuit. The I/O write-buffer driver circuit is coupled to a load current compensation circuit. Although each I/O buffer includes an I/O write-buffer circuit, a single load current compensation circuit may be coupled to several I/O write-buffer driver circuits. The load current compensation circuit generates a load compensation current for each I/O buffer circuit that is not being programmed. The load compensation current increases the load current so that a drain-side programming voltage (VPROG) drives a substantially constant load current, wherein the drain-side programming voltage is substantially independent of the number of bits being programmed.

Abstract: A memory device and a method for refreshing the memory device. The memory device includes a memory cell capable of storing two bits of data. One bit is referred to as the normal data bit and the other bit is referred to as the complementary data bit. Each memory cell has an associated dynamic reference cell. The normal data is refreshed by latching refresh data into a data latch and ORing the latched data with input data. The refresh data is written to the corresponding memory location. The data for the complementary data bit is refreshed by latching complementary data bit refresh data into the complementary data latches and writing to the memory cell. The normal and complementary data bits are refreshed before each read operation.

Abstract: In a method and system for providing a CAM (content addressable memory) cell of a flash memory device, a respective core flash memory cell to be used as the CAM cell is fabricated as part of a core array of the flash memory device. In addition, the respective core flash memory cell is accessed from the core array as the CAM cell for a CAM function within the flash memory device. Components used for supporting operation of the core array are also used for accessing the core flash memory cells of the additional sector for such CAM functionality. Thus, CAM functionality is provided with a minimized number of components and with minimized area of the die of the flash memory device. In addition, because the CAM cells are implemented as core flash memory cells of the core array, the CAM cells may reliably undergo more numerous programming and erasing cycles.

Abstract: A method of implementing a reference current measurement mode within a reference array programming mode or a reference array erase mode in a semiconductor chip is disclosed. This implementation leads to significant reduction in testing time for the semiconductor chip, increasing production volume and revenues.

Abstract: In a method and system for monitoring erase pulses applied on a sector of flash memory cells fabricated on a semiconductor substrate, a pulse counter and a pulse counter controller are fabricated on the semiconductor substrate. The pulse counter controller inputs a maximum number and outputs an indication of a sector fail if the flash memory cells of the sector do not pass erase verification with less than the maximum number of erase pulses applied on the sector during an erase verify BIST (Built-in-Self-Test) mode. In one example, the maximum number is a percentage of a diagonal total number of erase pulses needed to be applied on the sector until each flash memory cell at a diagonal location of the sector passes erase verification.

Abstract: In a method and system for repairing defective flash memory cells fabricated on a semiconductor substrate, a repair controller and a plurality of voltage sources are fabricated on the semiconductor substrate. The repair controller controls the voltage sources to apply programming voltages on respective CAM (content addressable memory) flash memory cells in a JUICE state for replacing the defective flash memory cells with a corresponding redundancy element of flash memory cells. In addition, a FAILREP logic is fabricated on the semiconductor substrate for entering a HANG state if no redundancy element of flash memory cells is available or if the defective flash memory cells have been previously repaired.

Abstract: A wait system for a memory device is operative to provide a wait signal to delay performance of each operation relative the memory cell. The wait signal initially delays performance of at least one initial operation relative the memory cell during a given user mode by a first duration. After the initial wait signal, a subsequent wait signal is provided to delay performance of subsequent operations relative the memory cell during the given user mode by a second duration, which is less than the first duration.

Abstract: Methods and apparatus are disclosed for verifying soft programming of one or more memory cells in a memory device. The methods comprise providing a voltage source to the core cell gate, and verifying soft programming of the cell after overshoot in the regulated voltage source has settled. Also disclosed are memory devices having a logic circuit providing a regulated voltage source to the cell gate during a soft program verify operation, and a sensor to verify soft programming of the cell when a first voltage is applied to the gate from the regulated voltage source. The logic circuit provides a soft program verify signal to the sensor to verify soft programming after overshoot in the voltage source has settled.

Abstract: A wait system for a memory device is operative to provide a wait signal to delay performance of each operation relative the memory cell. The wait signal initially delays performance of at least one initial operation relative the memory cell during a given user mode by a first duration. After the initial wait signal, a subsequent wait signal is provided to delay performance of subsequent operations relative the memory cell during the given user mode by a second duration, which is less than the first duration.

Abstract: A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.

Abstract: A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.

Abstract: When an array VT test mode is entered, a predetermined wordline voltage is generated by a wordline voltage supply and supplied to at least one decoder circuit and a voltage control logic circuit. The voltage control logic circuit generates a predetermined control voltage that is directed to the decoder circuits. The predetermined control voltage activates the decoder circuits. A particular decoder circuit is electrically selected to decode at least one respective wordline and transfer the predetermined wordline voltage to the respective wordline. The activated decoder circuits that are not electrically selected are not forward-biased.

Abstract: The present invention discloses methods and systems of wordline voltage protection to supply voltage to a plurality of wordlines in a memory device only during a read mode and a write mode. In the preferred embodiment, at least one wordline voltage protection circuit controls at least one decoder circuit that is activated to transfer voltage from at least one wordline voltage supply circuit to at least one wordline. The wordline voltage protection circuit activates the decoder circuit to transfer voltage to the wordline when the voltage is within a predetermined range and the memory device is performing one of a plurality of functions that include the write mode. The wordline voltage protection circuit also activates the decoder circuit to transfer voltage to the wordline when the memory device is performing one of a plurality of functions that include the read mode.

Abstract: The present invention discloses a method of providing a voltage to a plurality of wordlines during the Automatic Program Disturb Erase Verify (APDEV) operation in a memory device. During the APDEV operation, the voltage is supplied to the wordlines sequentially from two energy sources; a charge share circuit and a temperature compensated bias generator circuit. The respective voltages from the two energy sources are applied to the wordlines to charge the wordlines to a bias voltage. The bias voltage is the appropriate voltage on the wordlines to allow the memory device to verify that the bitline current flow is not excessive in the erased memory sector at the present operating temperature of the memory device. The amount of voltage needed to create the bias voltage is dependent on the operating temperature of the memory device.

Abstract: The present invention discloses systems and methods for providing voltages during programming to the control gates of write protect CAMS. Upon entering a write protect CAM programming mode, at least one voltage supply circuit is activated to supply the predetermined voltage for the control gates of the write protect CAMS. When the write protect CAMS are programmed, a gate control circuit transfers a programming voltage to the control gates of the write protect CAMS. Following programming and verification of the write protect CAMS, the gate control circuit holds the control gates of the write protect CAMS at a ground voltage level.