Abstract: A cable modem interface unit transmits packets to a packet source. The packet source sends control packets to a cable modem and requires a reply control packet in response to sending a control packet. The cable modem interface unit is coupled to the cable modem and a network driver interface layer. The interface unit generates a reply control packet in response to receiving a control packet from the cable modem. The reply control packet is queued in a transmit stack in the interface unit. The transmit stack includes data packets received from the network driver interface layer. The interface unit sends the reply control packet and the data packets from the stack to the cable modem so that they are eventually sent to the packet source.

Abstract: A cable modem interface unit is positioned between a cable modem and a network driver interface layer. The cable modem receives packets from a packet source. The interface unit includes a control packet filter coupled to the modem. The control packet filter receives a packet from the cable modem and determines whether the packet is a control packet or a data packet. The interface unit further includes a receive unit coupled to the control packet and the network driver interface layer. If the control packet filter determines that the packet is a data packet, the receive unit receives the packet from the control packet filter and sends the packet to the network driver interface layer. The interface unit further includes a protocol handler coupled to the receive unit. If the control packet filter determines that the packet is a control packet, the protocol handler receives the packet from the control packet filter.

Abstract: The present invention provides a novel multi-mode DRAM controller adaptd to access DRAM chips of a main storage unit of different size and of different mode types. The novel DRAM controller comprises new address generation and control logic for delaying the RAS and CAS control signals to memory and for expanding the number of address bits employed to address memory chips having a greater number of addresses by at least one address bit.