Patents by Inventor Edward William Olsen

Edward William Olsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10586757
    Abstract: A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: March 10, 2020
    Assignee: Linear Technology Corporation
    Inventor: Edward William Olsen
  • Publication number: 20170345744
    Abstract: A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.
    Type: Application
    Filed: May 27, 2016
    Publication date: November 30, 2017
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventor: Edward William Olsen
  • Patent number: 9691681
    Abstract: A method of making an integrated circuit package that contains a semiconductor die having one or more electrical connections to an electronic circuit within the semiconductor die. The method may include: encapsulating the semiconductor die and its electrical connections in non-electrically conductive, encapsulation material; laser drilling the encapsulation material to expose one of the electrical connections within the integrated circuit package, thereby creating a via opening in an external surface of the encapsulation material to the electrical connection; and electroplating or sputtering over the via opening in the encapsulation material to create a conductive routing layer from the exterior surface of the encapsulation material to the electrical connection.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: June 27, 2017
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventor: Edward William Olsen
  • Publication number: 20160260652
    Abstract: A method of making an integrated circuit package that contains a semiconductor die having one or more electrical connections to an electronic circuit within the semiconductor die. The method may include: encapsulating the semiconductor die and its electrical connections in non-electrically conductive, encapsulation material; laser drilling the encapsulation material to expose one of the electrical connections within the integrated circuit package, thereby creating a via opening in an external surface of the encapsulation material to the electrical connection; and electroplating or sputtering over the via opening in the encapsulation material to create a conductive routing layer from the exterior surface of the encapsulation material to the electrical connection.
    Type: Application
    Filed: May 13, 2016
    Publication date: September 8, 2016
    Applicant: LINEAR TECHNOLOGY CORPORATION
    Inventor: Edward William Olsen
  • Patent number: 9431319
    Abstract: An integrated circuit package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the integrated circuit package.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: August 30, 2016
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventors: Edward William Olsen, Leonard Shtargot, David Roy Ng, Jeffrey Kingan Witt
  • Publication number: 20160035645
    Abstract: A flipchip package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the flipchip package.
    Type: Application
    Filed: February 24, 2015
    Publication date: February 4, 2016
    Inventors: Edward William Olsen, David A. Pruitt, Gregory S. Peck, Leonard Shtargot
  • Publication number: 20160035644
    Abstract: An integrated circuit package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the integrated circuit package.
    Type: Application
    Filed: February 24, 2015
    Publication date: February 4, 2016
    Inventors: Edward William Olsen, Leonard Shtargot, David Roy Ng, Jeffrey Kingan Witt
  • Patent number: 8017447
    Abstract: A method of preparing a portion of the side of a terminal of an Integrated Circuit (IC) package for solder is disclosed. The method comprises the steps of attaching an IC die to a leadframe comprising a connecting bar, reducing the thickness of a portion of the connecting bar, overmolding the leadframe with a mold compound, removing the mold compound from the reduced-thickness portion of the connecting bar using a laser, coating the reduced-thickness portion of the connecting bar with a solder-wettable material, and cutting through the thickness of the connecting bar within the reduced thickness portion of the connecting bar, wherein the cut has a width that is less than the width of the reduced thickness portion of the connecting bar.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: September 13, 2011
    Assignee: Linear Technology Corporation
    Inventor: Edward William Olsen