Abstract: A polymer matrix defining pores is formed by polymerizing polymer precursors in a precursor solution. The precursor solution comprises a bicontinuous microemulsion of a first fluid in a first continuous phase and a second fluid in a second continuous phase. The first fluid comprises the polymer precursors. The second fluid comprises the glucose probe. Some internal pores are connected to surface pores in the matrix through openings sized to allow passage of glucose molecules but restrict passage of the glucose probe. As the glucose probe is dispersed in the precursor solution prior to polymerization, some glucose probe molecules are trapped in the internal pores after polymerization. The formed polymer may be used in an ophthalmic device such as contact lens, for detecting the presence of glucose in an ocular fluid.

Abstract: A bicontinuous microemulsion of water, a monomer, and a surfactant copolymerizable with the monomer is polymerized to form a transparent and porous polymer defining interconnected pores. The pores may have a pore diameter in the range of 10 to 100 mm. The microemulsion may further include a drug such that, when the polymer is formed, the drug is dispersed in one or both of the polymer and the pores and is releasable therefrom when the polymer is in contact with a liquid. The drug may be an ophthalmic drug and the polyer can be used to form drug delivery devices, such as contact lenses and artificial corneas.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Abstract: A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.