Abstract: Phase shift key modulators (100, 500, 1000, 1400, 1700) are provided in which a multiphase signal source (108, 1402, 1406-1412,1702) is used to generate a plurality of phases of a carrier signal. A selector (110) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source (102, 1422). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters (202). Preferably, a phase sequencer (502) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors (110, 1004) are used to simultaneously select two phases of carrier signal, and a phase interpolator (1106) is used to generate a sequence of phases from the two phases selected by the two phase selectors (110, 1004).

Abstract: Phase shift key modulators (100, 500, 1000, 1400, 1700) are provided in which a multiphase signal source (108, 1402, 1406-1412,1702) is used to generate a plurality of phases of a carrier signal. A selector (110) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source (102, 1422). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters (202). Preferably, a phase sequencer (502) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors (110, 1004) are used to simultaneously select two phases of carrier signal, and a phase interpolator (1106) is used to generate a sequence of phases from the two phases selected by the two phase selectors (110, 1004).

Abstract: Communication apparatus (100) corrects for amplitude imbalance caused by differences in circuitry that process in-phase and quadrature signals. The in-phase and quadrature signals are alternately routed in rapid succession through first and second parallel processing circuits or signal paths (140, 150) to cancel imbalances between the signal paths. Switches (132, 134) are employed at inputs to and outputs from corresponding portions of both signal paths, and these switches (132, 134) are synchronously operated in response to a control signal to interchange signals on the signal paths.

Abstract: A direct current (DC) offset correction loop (200) for determining the required amount of DC offset to an analog input signal includes a digital integrator (211) for measuring the amount of DC offset present at the final output of a forward signal path and a hold circuit (213) for controlling the digital integrator (213). The DC offset correction loop (200) provides a constant amount of DC offset correction to the analog input signal.

Abstract: A quadrature generator (100) includes a phase detector (125) having a set of differential inputs for coupling in-phase and quadrature signals (114,116) and a set of differential outputs for providing a phase error signal (135). Switches (122,127) are associated with the set of input terminals and with the set of output terminals. The switches (122,127) are synchronously controlled to switch around the signals at the input terminals and at the output terminals in concert, and in rapid succession. The operation of the switches (122,127) eliminates or reduces the effects of imperfections within the parallel paths of the phase detector circuitry (125), in order to produce a more accurate phase deviation signal.

Abstract: Second order intermodulation distortion (IM2) occurs when two interfacing signals mix with each other through a second order nonlinearity to produce an intermodulation product at the sum and difference frequencies of the two interferers. To reduce the amount of intermodulation distortion, dynamic matching is employed. In practice, dynamic matching operates to transform coefficients of IM2 distortion from constant values into functions of time where they may be handled by known rejection techniques.

Abstract: A baseband demodulator receives inphase and quadrature signals I (116) and Q (117) representing a phase angle and amplitude. The demodulator (114) includes a discrete time continuous amplitude circuit (223, 253, 260) coupled to the quadrature generator to extract a sign information by processing the quadrature components (116 and 118). An accumulator 404 uses the sign information to manipulate predetermined phase angles stored at a memory component 402 to determine the phase angle carried by the I and Q components (116 and 118). As such, the need for up converters or complex analog-to-digital converters is eliminated in direct conversion receivers.