Abstract: A RAM-based interrupt-driven interface device is disclosed for establishing a communication link between a universal serial bus (USB) host and a microcontroller device for providing a control function, the interface device being operative to receive digital information in the form of command, data and control packets from the host and to process the packets and communicate the processed digital information to the microcontroller device, and in response thereto, the microcontroller device being operative to communicate digital information to the interface device for processing and transfer thereof to the host.

Abstract: A novel architecture is based on a general purpose microcomputer with an "upstream" bus and a "downstream" bus. The upstream bus interfaces to an integrated multiport RAM that is shared between an upstream processor and the local processor, and possesses both upstream and local (downstream) interrupts associated with dedicated locations in RAM. The upstream bus can be operated in two modes, a standard (EISA) PC bus MASTER mode in which the dual port RAM is compatible with an IBM PC bus and a SLAVE mode in which the upstream bus is compatible with the downstream bus. An indefinitely long chain of such processors can be initialized by one host. Orthogonal channels (decoupled from the main upstream/downstream bus) can be used to achieve unique functionality based on host control of arrays of such processors.

Abstract: A remote communication system for facilitating secure on-line evaluation of goods based upon consumers' satisfaction through electronic media wherein a suitable local user input device in association with a data transmission system, couples the user input to a packet network system for communicating to a remote receiver/decoder apparatus to obtain potentially desired scoring information such as an electronic evaluation form regarding a previously purchased product. Upon selection of scoring option by the user, a telcom network communication link for communicating a telephone number associated with the desired product from the user to the remote receiver allows the user to score the desired product. The telcom connection, linking the user input device to the remote server device may also include a toll-free 800 telephone number system to encourage shoppers to perform evaluations of purchased product without incurring costs associated therewith.

Abstract: A microcontroller down-loadable memory organization supporting "shadow" personality, optimized for connecting a computer system to an ISDN network to facilitate transmitting and receiving of data, the microcontroller including a processor and a memory structure having ROM memory space for storing program code therein and further including a dual port RAM for connection between the computer and the processor, the dual port RAM having RAM memory space for storing program code therein and shared RAM for storing data capable of being simultaneously accessible by the processor and the computer, wherein the program ROM and the program RAM are selectively used by the computer to store program code by the computer using a ROM/RAM* select signal, and wherein the starting address in the shared RAM wherein data is stored is selectably offset from the starting address of the code RAM and the code ROM.

Abstract: A remote communication system for facilitating secure electronic sales of products, wherein a suitable seller input device in association with a local seller data transmission system couples the seller to a packet network system for communicating to a remote receiver/decoder apparatus to download registration data to the seller system. Upon retrieving a telephone toll number from the remote apparatus, a telcom network communication link for communicating the telephone number from the seller to the remote receiver allows the seller to upload the product that is to be offered for sale to the remote apparatus. The telcom connection, linking the seller system to the remote apparatus may also include a 900 number billing system whereby a fee is assessed and charged at a rate determined by the toll connection provider after uploading the product.

Abstract: A remote communication system for facilitating secure electronic purchases of goods in on-line, wherein a suitable local user input device in association with a data transmission system, couples the user input into a packet network system for communication to a remote receiver/decoder apparatus to TRY a potentially desired product. Upon selection of the desired product by the user, a telcom network link is used to communicate a telephone number associated with the desired product from the user to the remote receiver to allow the user to BUY the desired product. The telcom network used to link the user input device to the remote apparatus may also include a 900 number billing system for assessing and collecting fees for use of the system.

Abstract: The present invention is directed to an apparatus and method that provides a universal call processing system to process all possible data types transmitted over an ISDN telephone line. A universal call processing system generally comprises an ISDN interface subsystem, a call control subsystem, a call processing subsystem, a controller state machine, and user interface devices.

Abstract: Ring communication system using ISDN including terminal adapter hardware and associated software that can be combined with a general purpose computer and used to provide a work station or party unit which can be linked together with other similarly configured units via the ISDN to provide a closed wide area network. Although the system can be implemented on any type of computer using any programming language, in the preferred embodiment proprietary software designated WinISDN.DLL in a Microsoft Windows.TM. environment is used to implement a novel algorithm in Visual Basic or C-language programming systems. The hardware aspects of the invention are provided in a terminal adapter card that includes a dual port RAM, an ISDN controller, and a subscriber access controller. The adapter card plugs into the (E)ISA bus that is the PC standard bus/backplane.

Abstract: A system with source and destination telecommunications transceivers for communicating therebetween over an Integrated Digital Services Network, each having a general purpose computer coupled to an interface circuit for conditioning outgoing and incoming data to and from the communications network. The interface circuit is constructed with a dual port RAM, a subscriber access controller and an ISDN controller. A typical data flow proceeds with the source controller CPU sending bytes of data from a sending buffer in its memory to a first transmit buffer in the dual port RAM. This process continues until the last address in the buffer is filled, whereupon the dual port RAM outputs an interrupt signal to the ISDN controller which responds by sending the data bytes in the buffer to the subscriber access controller for transmission to the ISDN, and sends a control signal instructing the computer to load a second transmit buffer.

Abstract: A data transmission and control system using local, externally generated D, Q, M bits in X.25 packets, and including a controller, a controlled device and a transceiver module at each of a plurality of locations. The controller at each location generates and delivers user controlled D, Q and M bits on separate lines and other data on an input/output data bus to the transceiver. The transceiver receives the Q, D, M bits and other data and assembles the data bits with other standard organizational bits to form X.25 information packets according to X.25 protocol. An ISDN interface then inserts the X.25 information packets in standard 48 bit frames for transmission over the ISDN network. The D, Q, M bits and other data are then received at a remote location where the process is reversed, the transceiver receiving the X.

Abstract: A digital signal processing apparatus including a graphic template display including an input circuit for sampling, digitizing and storing successive samples of an input signal, a signal processor for scaling the sampled signal data, a buffer for storing the scaled signals, a copy memory for storing a copy of the scaled signal data, a template memory for storing template data, an image retrieval circuit for accessing and reading out the stored signal and template data, a data mapping circuit for reformatting the stored image data, a display memory for holding the reformatted image data for cyclical display, a memory access circuit for accessing and combining the reformatted image data and the display memory data, and for providing the timing necessary for presentation of the combined data, and display apparatus for displaying the combined data in an original format.

Abstract: A ISDN "S" signal detection and display apparatus including a clock signal generator for synchronizing to the "S signal" and for developing a frame sync clock, a signal converter for connection across the "S" interface to develop a "clean" digital signal corresponding to S-signals received at the "S" interface, a signal processor responsive to the frame sync clock and operative to sample successive S-signals, a storage buffer for temporarily storing the sampled signals, and a display for reporting and/or displaying the averaged signals.

Abstract: A recognition system for robots is responsive to encoded information from a plurality of sources for enabling a robot to recognize and identify the sources. A receiver located on the robot detects incoming signals and decodes them. The decoded signal is compared with information stored in the robot memory to provide source identification. A direction determining sub-system incorporated into the receiver provides source direction information. The system may utilize either digital or analog techniques.

Abstract: An electronic optical analyzer for use in systems such as optical transfer function analyzers eliminates mechanical scanning systems and comprises entirely electronic image dissection means for dissecting an image transmitted by an optical system under test and producing an electric output signal representative of the beam intensity at a selected element of the image. The image dissection means is preferably (in the case of visible light) an image dissector tube whose positioning coils serve as an image element addressing means. The system is useable with any optical system including visible light, other electromagnetic radiation or charged particles (ions or electrons) so long as the image dissection means is responsive to the beam in question. The optical system under test must produce a real image at the image dissection surface of the image dissection means in order for readily evaluatable data to be obtained.