Abstract: Examples include techniques associated with data movement to a cache in a disaggregated die system. Examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. The granting of the request based, at least in part, on a traffic source type associated with a source of the request.

Abstract: A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.

Abstract: A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.

Abstract: A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.

Abstract: A method for determining Internet access by an autonomous electronic circuit on a system on a chip integrated circuit includes a system bus which is snooped to determine if Internet activity is occurring on the system bus. Local header information is collected when the snooping has determined that Internet activity is occurring on the system bus. A packet including the local header information is created. Internet access is requested with the created packet.

Abstract: An apparatus, system and method is disclosed herein for searching and retrieving data in the form of text and images that may be used for designing and drawings applications in industry and for crime investigation and prevention. Data is retrieved from databases optionally using a statistical profiler and observations/hunch notes to filter and narrow the search. The present invention may serve as a simulation tool, as a storage system, as a legal presentation system and as a calculation program.

Abstract: A method and apparatus for transmitting data packets in an integrated circuit according to a data integrity scheme that embeds an integrity value in each data packet. As the data packets are transferred, the data integrity value for a data packet is stored during a stall of the transmission of that data packet so that the stored integrity value can be used after the stall has ceased.

Abstract: A computer system is disclosed which includes a design structure including a CPU or microprocessor to drive tightly constrained hardware events. The system comprises a processor having a set of system inputs to drive a functionally programmable event, and a fast branch in the CPU including a state handler to execute instructions from the CPU to process the event. A queue in the CPU stores the events such that the non-pre-empted events are serviced in the order they are received.

Abstract: A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.

Abstract: A universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.

Abstract: An enhanced video conferencing system and method includes at least two conference rooms, the conference rooms connected together electronically to permit the transmission of images and sound from one room to the other room. Each room has a large format display system for projecting images and a camera positioned with respect to the large format display system to capture images of the conference room and its participants while the participants are looking at the large format display system, without obscuring the participants' view of the display system, so as to provide the perception that the participants in one conference room are looking directly at the participants in the other conference room. The enhanced video conferencing system may also include an additional camera for capturing an image of an item located at a pre-determined location within the conference room for ultimate transmission to the other conference room for viewing.

Abstract: A method and apparatus are provided for implementing communications in a communications network. The apparatus for implementing communications includes a system interface to the communications network. A scheduler schedules enqueued cells and enqueued frames to be transmitted. A segmenter segments frames and cells in into cells or frames applied to a media adaptation block for transmission in a selected one of multiple modes.

Abstract: A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.

Abstract: A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also described is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.

Abstract: A method for translating a virtual address into a physical address, in which page tables used in the translation process are referenced by virtual addresses. Typically, a translation mechanism includes a translation buffer that, given a virtual address, can sometimes provide the corresponding physical address. A translation-buffer miss is said to occur when the translation buffer is presented with an address for which it can not provide the translation. When such a miss occurs, the translation mechanism obtains the translation by reading the page tables. When the translation mechanism attempts to read the page tables from virtual memory, a second-order miss can occur. The difficulty of infinite recursion of misses is avoided by handling second-order misses differently from first-order misses. When a second-order miss occurs, the translation mechanism uses a prototype page table entry and the virtual address of the page table entry to produce a physical address without using the page tables.