Abstract: An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device's on-board FPGA and the firmware code for the interface device's microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configured, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code.

Abstract: An interface board and inserted modular IC interface cards allows variable length boundary scan chains. The chain can be constructed of any type of programmable integrated circuit (IC) in any order. The interface board contains a plurality of JTAG interfaces that respectively mate with standard adapter interfaces located on the modular IC interface cards. If less than the maximum number of modular IC interface cards are inserted into the interface board, a terminator card is inserted into the standard interface following the last modular IC interface card of the chain. The last test data output signal of the chain is routed back to a connector of the interface board. The interface board includes an output cascade connector that couples with an input cascade connector of another interface board so that any number of interface boards can be cascaded in series to expand the boundary scan chain.

Abstract: A method is disclosed for alerting a user of a low power condition on, for instance, an FPGA interface device. An interface device having a microcontroller and an associated power plane for powering the microcontroller and other component on the interface device includes a detection circuit coupled to monitor the voltage level of the associated power plane. When the voltage level of the voltage plane falls below a predetermined threshold voltage, the detection circuit sends a low power flag to a host system. The low power flag, which is preferably sent to the host system using a USB port connection, alerts the host system of the low power condition on the interface device. The predetermined threshold voltage is selected to be a suitable amount higher than the minimum operating voltage for the microcontroller so as to allow sufficient time for the microcontroller to send the low power flag to the host system.

Abstract: A method in accordance with the present invention includes programming a plurality of semiconductor devices simultaneously, thereby dramatically increasing the number of devices programmed within a predetermined time. In one embodiment, this method includes arranging a first plurality of semiconductor devices into an array configuration. The first array is then programmed while a second plurality of semiconductor devices is arranged into the array configuration. The second array is then programmed, while the first array is unloaded and a third plurality of semiconductor devices is arranged into the array configuration. The present invention further includes the step of moving the first plurality of semiconductor devices in the array configuration to a programming position and the step of transferring the first plurality of semiconductor devices to an unloading position.

Abstract: A method in accordance with the present invention includes programming a plurality of semiconductor devices simultaneously, thereby dramatically increasing the number of devices programmed within a predetermined time. In one embodiment, this method includes arranging a first plurality of semiconductor devices into an array configuration. The first array is then programmed while a second plurality of semiconductor devices is arranged into the array configuration. The second array is then programmed, while the first array is unloaded and a third plurality of semiconductor devices is arranged into the array configuration. The present invention further includes the step of moving the first plurality of semiconductor devices in the array configuration to a programming position and the step of transferring the first plurality of semiconductor devices to an unloading position.

Abstract: An emulator probe assembly for testing circuit boards which control programmable logic devices includes a header assembly, a universal pod, and an extender. The header assembly includes a socket, a plug, and a flexible cable. The header socket is matched in size to the socket of the circuit board so that during testing the programmable logic device can be inserted into the header socket and the header plug into the circuit board. Some pins in the header plug are connected directly to crresponding pins in the header socket. However other pins in the header plug are connected through lines in the flexible cable to contacts in a pod plug at the opposite end of the flexible cable. Corresponding pins in the header socket are also connected through the flexible cable to contacts in the pod plug. The pod plug is received by the universal pod which has electronics for controlling or receiving signals from the programmable logic device or the circuit board.