Abstract: A signal receiver includes a current source providing a current having a current value, a pair of active input devices, and a pair of resistors. Each active input device includes a control node, a first conduction node, and a second conduction node. One of the control nodes receives an input signal. The first conduction nodes are connected to each other and receive the current. One of the second conduction nodes serves as an output node. The active input devices output an output signal to a core circuit according to the current and the input signal. Each resistor has a resistance value. A target voltage value is determined according to the resistance value and the current value, such that a voltage swing of the output signal is limited within the target voltage value, and an operating voltage of the core circuit is substantially equal to the target voltage value.

Abstract: A driving circuit includes a first driving module, configured to operate at a first operating voltage in a first mode and configured to be deactivated in a second mode; and a second driving module, wherein at least part of the second driving module operates at a protection voltage in the first mode and operates at a second operating voltage in the second mode, wherein the second operating voltage and the protection voltage are lower than the first operating voltage.

Abstract: A driving circuit includes a first driving module, configured to operate at a first operating voltage in a first mode and configured to be deactivated in a second mode; and a second driving module, wherein at least part of the second driving module operates at a protection voltage in the first mode and operates at a second operating voltage in the second mode, wherein the second operating voltage and the protection voltage are lower than the first operating voltage.

Abstract: A ball grid array formed on a printed circuit board is provided. The ball grid array includes a first bailout module and a second bailout module. The first bailout module includes a plurality of first solder balls arranged as an array. Two of the first solder balls are grounded, and remaining of the first solder balls are disposed within a shielding area defined by the two grounded first balls. Two among the second solder balls are grounded, and remaining of the second solder balls are disposed within a shielding area of the two grounded second balls. The first and second bailout modules deploy substantially a same bailout arrangement, which is associated with relative positions of the two grounded solder balls and the remaining solder balls that are not grounded in each bailout module.

Abstract: A signal receiver includes a current source providing a current having a current value, a pair of active input devices, and a pair of resistors. Each active input device includes a control node, a first conduction node, and a second conduction node. One of the control nodes receives an input signal. The first conduction nodes are connected to each other and receive the current. One of the second conduction nodes serves as an output node. The active input devices output an output signal to a core circuit according to the current and the input signal. Each resistor has a resistance value. A target voltage value is determined according to the resistance value and the current value, such that a voltage swing of the output signal is limited within the target voltage value, and an operating voltage of the core circuit is substantially equal to the target voltage value.

Abstract: A driving circuit includes a first driving module, configured to operate at a first operating voltage in a first mode and configured to be deactivated in a second mode; and a second driving module, wherein at least part of the second driving module operates at a protection voltage in the first mode and operates at a second operating voltage in the second mode, wherein the second operating voltage and the protection voltage are lower than the first operating voltage.

Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

Abstract: An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end.

Abstract: The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data according to the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.

Abstract: A ball grid array formed on a printed circuit board is provided. The ball grid array includes a first bailout module and a second bailout module. The first bailout module includes a plurality of first solder balls arranged as an array. Two of the first solder balls are grounded, and remaining of the first solder balls are disposed within a shielding area defined by the two grounded first balls. Two among the second solder balls are grounded, and remaining of the second solder balls are disposed within a shielding area of the two grounded second balls. The first and second bailout modules deploy substantially a same bailout arrangement, which is associated with relative positions of the two grounded solder balls and the remaining solder balls that are not grounded in each bailout module.

Abstract: A universal IO unit applied to a chip or an integrated circuit is provided. The universal IO unit includes a power pad and a plurality of signal pads for providing different functions. According to functional requirements of the universal IO unit, the pad power is selectively connected to an electric wire to couple to a predetermined voltage, and each of the signal pads is also selectively connected to a signal wire to transceive signals.

Abstract: The data access apparatus comprises a phase locked loop (PLL) and a data receiving circuit. The PLL provides a plurality of internal clocks and selecting a strobe clock from the plurality of internal clocks according to a phase selection signal. The data receiving circuit comprises a latching module, for latching of the data signal according to trigger of the strobe clock and a calibrating circuit, for generating the phase selection signal for matching the data with a predetermined data at the plurality of internal clocks in a training mode and finally determining the phase selection signal corresponding to a preferred clock used in a normal mode.

Abstract: A universal IO unit applied to a chip or an integrated circuit is provided. The universal IO unit includes a power pad and a plurality of signal pads for providing different functions. According to functional requirements of the universal IO unit, the pad power is selectively connected to an electric wire to couple to a predetermined voltage, and each of the signal pads is also selectively connected to a signal wire to transceive signals.

Abstract: A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

Abstract: An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end.

Abstract: A method and apparatus for managing hysterisis in a delay line. In one embodiment, an integrated circuit includes a delay line. A selection circuit is coupled to an input of the delay line. The selection circuit includes two inputs: a first input coupled to convey a signal such as a data signal or a data strobe signal, while the second input is coupled to convey a dummy clock signal. Control logic is coupled to monitor activity within the delay line. Upon detecting a lack of activity for a predetermined time period, the control logic is configured to cause the selection circuit to allow the dummy clock signal to be conveyed to the input of the delay line.