Patents by Inventor Efe Sinan Ege
Efe Sinan Ege has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11882774Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.Type: GrantFiled: September 7, 2021Date of Patent: January 23, 2024Assignee: Micron Technology, Inc.Inventors: Rajasekhar Venigalla, Patrick M. Flynn, Josiah Jebaraj Johnley Muthuraj, Efe Sinan Ege, Kevin Lee Baker, Tao Nguyen, Davis Weymann
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Patent number: 11778837Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.Type: GrantFiled: June 22, 2022Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventors: Lei Wei, Pengyuan Zheng, Kevin Lee Baker, Efe Sinan Ege, Adam Thomas Barton, Rajasekhar Venigalla
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Publication number: 20220406847Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.Type: ApplicationFiled: June 22, 2022Publication date: December 22, 2022Inventors: Lei Wei, Pengyuan Zheng, Kevin Lee Baker, Efe Sinan Ege, Adam Thomas Barton, Rajasekhar Venigalla
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Patent number: 11380732Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.Type: GrantFiled: July 29, 2020Date of Patent: July 5, 2022Assignee: Micron Technology, Inc.Inventors: Lei Wei, Pengyuan Zheng, Kevin Lee Baker, Efe Sinan Ege, Adam Thomas Barton, Rajasekhar Venigalla
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Publication number: 20220069216Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.Type: ApplicationFiled: September 7, 2021Publication date: March 3, 2022Inventors: Rajasekhar Venigalla, Patrick M. Flynn, Josiah Jebaraj Johnley Muthuraj, Efe Sinan Ege, Kevin Lee Baker, Tao Nguyen, Davis Weymann
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Publication number: 20220037403Abstract: A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.Type: ApplicationFiled: July 29, 2020Publication date: February 3, 2022Inventors: Lei Wei, Pengyuan Zheng, Kevin Lee Baker, Efe Sinan Ege, Adam Thomas Barton, Rajasekhar Venigalla
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Patent number: 11121317Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.Type: GrantFiled: November 14, 2019Date of Patent: September 14, 2021Assignee: Micron Technology, Inc.Inventors: Rajasekhar Venigalla, Patrick M. Flynn, Josiah Jebaraj Johnley Muthuraj, Efe Sinan Ege, Kevin Lee Baker, Tao Nguyen, Davis Weymann
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Publication number: 20210151675Abstract: Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.Type: ApplicationFiled: November 14, 2019Publication date: May 20, 2021Inventors: Rajasekhar Venigalla, Patrick M. Flynn, Josiah Jebaraj Johnley Muthuraj, Efe Sinan Ege, Kevin Lee Baker, Tao Nguyen, Davis Weymann