Patents by Inventor Ehud Trainin
Ehud Trainin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9600347Abstract: A computer implemented system and method for measuring synchronization coverage for one or more concurrently executed threads is provided. The method comprises updating an identifier of a first thread to comprise an operation identifier associated with a first operation, in response to determining that the first thread has performed the first operation; associating the identifier of the first thread with one or more resources accessed by the first thread; and generating a synchronization coverage model by generating a relational data structure of said one or more resources, wherein a resource is associated with at least the identifier of the first thread and an identifier of a second thread identifier, such that the second thread waits for the first thread before accessing said resource.Type: GrantFiled: November 26, 2009Date of Patent: March 21, 2017Assignee: International Business Machines CorporationInventors: Rachel Tzoref, Eitan Daniel Farchi, Ehud Trainin, Aviad Zlotnick
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Patent number: 9569343Abstract: A computer-implemented method for test planning and test case generation, includes collecting, by a processor, a plurality of requirements, creating, by the processor, a plurality of content space specification files that includes the plurality of requirements, processing, by the processor, the plurality of content space specification files to generate a plurality of user stories, outputting, by the processor, the plurality of user stories and integrating, by the processor, the user stories into test planning and test case generation.Type: GrantFiled: September 30, 2014Date of Patent: February 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward B. Boden, Itai Segall, Ehud Trainin
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Patent number: 9111040Abstract: A computer-implemented method for test planning and test case generation, includes collecting, by a processor, a plurality of requirements, creating, by the processor, a plurality of content space specification files that includes the plurality of requirements, processing, by the processor, the plurality of content space specification files to generate a plurality of user stories, outputting, by the processor, the plurality of user stories and integrating, by the processor, the user stories into test planning and test case generation.Type: GrantFiled: January 15, 2013Date of Patent: August 18, 2015Assignee: International Business Machines CorporationInventors: Edward B. Boden, Itai Segall, Ehud Trainin
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Publication number: 20150020053Abstract: A computer-implemented method for test planning and test case generation, includes collecting, by a processor, a plurality of requirements, creating, by the processor, a plurality of content space specification files that includes the plurality of requirements, processing, by the processor, the plurality of content space specification files to generate a plurality of user stories, outputting, by the processor, the plurality of user stories and integrating, by the processor, the user stories into test planning and test case generation.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Edward B. Boden, Itai Segall, Ehud Trainin
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Publication number: 20140201712Abstract: A computer-implemented method for test planning and test case generation, includes collecting, by a processor, a plurality of requirements, creating, by the processor, a plurality of content space specification files that includes the plurality of requirements, processing, by the processor, the plurality of content space specification files to generate a plurality of user stories, outputting, by the processor, the plurality of user stories and integrating, by the processor, the user stories into test planning and test case generation.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward B. Boden, Itai Segall, Ehud Trainin
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Patent number: 8561030Abstract: A method for enhancing synchronization coverage for a logic code is provided. The method comprises tracking whether one or more code sections in the logic code are blocked by at least another code section in the logic code, or whether one or more code sections in the logic code are blocking at least another code section in the logic code, during one or more test runs; and including one or more delay mechanisms in the logic code to introduce a delay in execution of a first code section in the logic code, wherein length of introduced delay is dependent on whether the first code section was blocked by a second code section or whether the first code section was blocking the second code section.Type: GrantFiled: December 14, 2009Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Ehud Trainin, Rachel Tzoref, Aviad Zlotnick
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Patent number: 8561031Abstract: A method for enhancing synchronization coverage for a logic code is provided. The method comprises tracking whether one or more code sections in the logic code are blocked by at least another code section in the logic code, or whether one or more code sections in the logic code are blocking at least another code section in the logic code, during one or more test runs; and including one or more delay mechanisms in the logic code to introduce a delay in execution of a first code section in the logic code, wherein length of introduced delay is dependent on whether the first code section was blocked by a second code section or whether the first code section was blocking the second code section.Type: GrantFiled: September 12, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Ehud Trainin, Rachel Tzoref, Aviad Zlotnick
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Publication number: 20130247062Abstract: A computer implemented system and method for measuring synchronization coverage for one or more concurrently executed threads is provided. The method comprises updating an identifier of a first thread to comprise an operation identifier associated with a first operation, in response to determining that the first thread has performed the first operation; associating the identifier of the first thread with one or more resources accessed by the first thread; and generating a synchronization coverage model by generating a relational data structure of said one or more resources, wherein a resource is associated with at least the identifier of the first thread and an identifier of a second thread identifier, such that the second thread waits for the first thread before accessing said resource.Type: ApplicationFiled: September 11, 2012Publication date: September 19, 2013Applicant: INTERNATIONAL BUSINESS MACHINESInventors: Rachel Tzoref, Eitan Daniel Farchi, Ehud Trainin, Aviad Zlotnick
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Publication number: 20130014087Abstract: A method for enhancing synchronization coverage for a logic code is provided. The method comprises tracking whether one or more code sections in the logic code are blocked by at least another code section in the logic code, or whether one or more code sections in the logic code are blocking at least another code section in the logic code, during one or more test runs; and including one or more delay mechanisms in the logic code to introduce a delay in execution of a first code section in the logic code, wherein length of introduced delay is dependent on whether the first code section was blocked by a second code section or whether the first code section was blocking the second code section.Type: ApplicationFiled: September 12, 2012Publication date: January 10, 2013Applicant: INTERNATIONAL BUSINESS MACHINESInventors: Ehud Trainin, Rachel Tzoref, Aviad Zlotnick
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Publication number: 20110145796Abstract: A method for enhancing synchronization coverage for a logic code is provided. The method comprises tracking whether one or more code sections in the logic code are blocked by at least another code section in the logic code, or whether one or more code sections in the logic code are blocking at least another code section in the logic code, during one or more test runs; and including one or more delay mechanisms in the logic code to introduce a delay in execution of a first code section in the logic code, wherein length of introduced delay is dependent on whether the first code section was blocked by a second code section or whether the first code section was blocking the second code section.Type: ApplicationFiled: December 14, 2009Publication date: June 16, 2011Applicant: International Business Machines CorporationInventors: Ehud Trainin, Aviad Zlotnick
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Publication number: 20110126173Abstract: A computer implemented system and method for measuring synchronization coverage for one or more concurrently executed threads is provided. The method comprises updating an identifier of a first thread to comprise an operation identifier associated with a first operation, in response to determining that the first thread has performed the first operation; associating the identifier of the first thread with one or more resources accessed by the first thread; and generating a synchronization coverage model by generating a relational data structure of said one or more resources, wherein a resource is associated with at least the identifier of the first thread and an identifier of a second thread identifier, such that the second thread waits for the first thread before accessing said resource.Type: ApplicationFiled: November 26, 2009Publication date: May 26, 2011Applicant: International Business Machines CorporationInventors: Rachel Tzoref, Eitan Daniel Farchi, Ehud Trainin, Aviad Zlotnick
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Patent number: 6757802Abstract: A computer system for allocating memory comprises a central processing unit (CPU) for controlling said system, a local memory for said CPU, means for allocating a plurality of memory blocks to tasks executed on said CPU, and block headers for said memory blocks. The block header further comprises a free block header comprising addresses of free memory blocks designated by the free block header, and further comprising an allocated block header including addresses of allocated memory blocks designated by said allocated block header.Type: GrantFiled: April 3, 2001Date of Patent: June 29, 2004Assignee: P-Cube Ltd.Inventors: Ehud Trainin, Assaf Zeira
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Publication number: 20020144073Abstract: A computer system for allocating memory comprises a central processing unit (CPU) for controlling said system, a local memory for said CPU, means for allocating a plurality of memory blocks to tasks executed on said CPU, and block headers for said memory blocks. The block header further comprises a free block header comprising addresses of free memory blocks designated by the free block header, and further comprising an allocated block header including addresses of allocated memory blocks designated by said allocated block header.Type: ApplicationFiled: April 3, 2001Publication date: October 3, 2002Inventors: Ehud Trainin, Assaf Zeira