Patents by Inventor Eifu Nezu

Eifu Nezu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11509955
    Abstract: A display system includes: a plurality of secondary display units that respectively display a plurality of videos; a primary display unit that displays at least one of the plurality of videos; a detection unit that detects a number of viewers of each of the plurality of secondary display units; and a control unit that causes the primary display unit to display a same video as the video being displayed by the secondary display unit having a highest number of viewers among the plurality of secondary display units, based on the numbers of viewers detected by the detection unit.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: November 22, 2022
    Assignee: SHARP NEC DISPLAY SOLUTIONS, LTD.
    Inventor: Eifu Nezu
  • Patent number: 11438652
    Abstract: A display system includes a main display unit configured to display a video; a plurality of subordinate display units configured to display a plurality of videos, respectively; a detection unit configured to detect the number of viewers of the main display unit and the respective numbers of viewers of the plurality of subordinate display units; and a control unit. The control unit is configured to switch a video displayed on a subordinate display unit of the plurality of subordinate display units to the same video as a video displayed on the main display unit when the number of viewers of the main display unit detected by the detection unit is equal to or more than a first predetermined value and the number of viewers of the subordinate display unit is less than a second predetermined value.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: September 6, 2022
    Assignee: SHARP NEC DISPLAY SOLUTIONS, LTD.
    Inventor: Eifu Nezu
  • Publication number: 20220222589
    Abstract: A display management device includes an acquisitioner and a data processor. The acquisitioner acquires occupancy request information from a first terminal. The occupancy request information indicates that a request is made to display content on a plurality of displays positioned in a first region. When the acquisitioner acquires the occupancy request information, the data processor generates a available time display data using a display information storage and transmits same to the first terminal. The display information storage stores information relating to available time of the plurality of displays positioned in the first region. The available time display data is data for displaying a screen which shows availability information including the number of displays which can be reserved and/or the occupancy rate thereof for each time period.
    Type: Application
    Filed: February 7, 2020
    Publication date: July 14, 2022
    Inventor: Eifu NEZU
  • Publication number: 20210321161
    Abstract: A display system includes a main display unit configured to display a video; a plurality of subordinate display units configured to display a plurality of videos, respectively; a detection unit configured to detect the number of viewers of the main display unit and the respective numbers of viewers of the plurality of subordinate display units; and a control unit. The control unit is configured to switch a video displayed on a subordinate display unit of the plurality of subordinate display units to the same video as a video displayed on the main display unit when the number of viewers of the main display unit detected by the detection unit is equal to or more than a first predetermined value and the number of viewers of the subordinate display unit is less than a second predetermined value.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventor: Eifu NEZU
  • Publication number: 20210144438
    Abstract: A display system includes: a plurality of secondary display units that respectively display a plurality of videos; a primary display unit that displays at least one of the plurality of videos; a detection unit that detects a number of viewers of each of the plurality of secondary display units; and a control unit that causes the primary display unit to display a same video as the video being displayed by the secondary display unit having a highest number of viewers among the plurality of secondary display units, based on the numbers of viewers detected by the detection unit.
    Type: Application
    Filed: May 31, 2018
    Publication date: May 13, 2021
    Inventor: Eifu NEZU
  • Patent number: 8422814
    Abstract: Unnecessary flare correction at the boundary between a blanking area and video signal area is suppressed. An image quality improving apparatus includes 2-dimensional low-pass filter circuit 2 that extracts low-frequency components from an input video signal; subtractor circuit 4 that obtains high-frequency components by subtracting the low-frequency components extracted by 2-dimensional low-pass filter circuit 2 from the input video signal; and adder circuit 6 that adds the high-frequency components obtained by subtractor circuit 4 as a correction signal to the input video signal. The input video signal contains blanking signals without any video information. 2-dimensional low-pass filter circuit 2 starts extraction of the low-frequency components after a lapse of a predetermined unit time from when the input video signal changed from the blanking signal to the signal that contains the video information.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: April 16, 2013
    Assignee: NEC Display Solutions, Ltd.
    Inventor: Eifu Nezu
  • Publication number: 20090279806
    Abstract: Unnecessary flare correction at the boundary between a blanking area and video signal area is suppressed. An image quality improving apparatus includes 2-dimensional low-pass filter circuit 2 that extracts low-frequency components from an input video signal; subtractor circuit 4 that obtains high-frequency components by subtracting the low-frequency components extracted by 2-dimensional low-pass filter circuit 2 from the input video signal; and adder circuit 6 that adds the high-frequency components obtained by subtractor circuit 4 as a correction signal to the input video signal. The input video signal contains blanking signals without any video information. 2-dimensional low-pass filter circuit 2 starts extraction of the low-frequency components after a lapse of a predetermined unit time from when the input video signal changed from the blanking signal to the signal that contains the video information.
    Type: Application
    Filed: January 25, 2008
    Publication date: November 12, 2009
    Inventor: Eifu Nezu
  • Patent number: 7518660
    Abstract: A field delay circuit aligns the phases of two field signals. An average value calculation circuit generates an average value signal of the two field signals. This average value signal can be regarded as a signal that has undergone a one-dimensional low-pass filter process in the row direction in which the number of taps for a progressive signal is 2 and the filter coefficient for each tap is 0.5 and that has then been thinned to one-half the data. A two-dimensional LPF circuit subjects this average value signal to a low-pass filter process and eliminates the high-frequency components (edge components). A subtraction circuit subtracts the average value signal that has undergone the LPF process from each field signal and thus extracts the edge components of each field signal. An amplification circuit multiplies the edge components of each field signal by a prescribed factor. An addition circuit adds the resulting amplified edge components to each field signal.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: April 14, 2009
    Assignee: NEC Viewtechnology, Ltd.
    Inventors: Michio Kobayashi, Eifu Nezu
  • Patent number: 7505084
    Abstract: An average value signal of the G two-phase input signal is generated by means of an average value calculation circuit. This average value signal is regarded as a signal in which a one-dimensional low-pass filter process, in which the number of taps is 2 and the filter coefficient for each tap is 0.5, has been carried out for a single-phase signal and the number of items of data then thinned to one half. A two-dimensional LPF circuit next subjects this average value signal to a low-pass filter process to eliminate the high-frequency component (edge component). The average value signal that has undergone the low-pass filter process is then subtracted from the input signal of each phase to extract the edge component of the input signal of each phase. An amplification circuit then multiplies the edge component of the input signal of each phase by a prescribed factor, and an addition circuit next adds this multiplied edge component to the input signal of each phase.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: March 17, 2009
    Assignee: NEC Viewtechnology, Ltd.
    Inventors: Michio Kobayashi, Eifu Nezu, Reiichi Kobayashi
  • Publication number: 20060103763
    Abstract: A field delay circuit aligns the phases of two field signals. An average value calculation circuit generates an average value signal of the two field signals. This average value signal can be regarded as a signal that has undergone a one-dimensional low-pass filter process in the row direction in which the number of taps for a progressive signal is 2 and the filter coefficient for each tap is 0.5 and that has then been thinned to one-half the data. A two-dimensional LPF circuit subjects this average value signal to a low-pass filter process and eliminates the high-frequency components (edge components). A subtraction circuit subtracts the average value signal that has undergone the LPF process from each field signal and thus extracts the edge components of each field signal. An amplification circuit multiplies the edge components of each field signal by a prescribed factor. An addition circuit adds the resulting amplified edge components to each field signal.
    Type: Application
    Filed: November 15, 2005
    Publication date: May 18, 2006
    Applicant: NEC Viewtechnology, Ltd.
    Inventors: Michio Kobayashi, Eifu Nezu
  • Publication number: 20060098122
    Abstract: An average value signal of the G two-phase input signal is generated by means of an average value calculation circuit. This average value signal is regarded as a signal in which a one-dimensional low-pass filter process, in which the number of taps is 2 and the filter coefficient for each tap is 0.5, has been carried out for a single-phase signal and the number of items of data then thinned to one half. A two-dimensional LPF circuit next subjects this average value signal to a low-pass filter process to eliminate the high-frequency component (edge component). The average value signal that has undergone the low-pass filter process is then subtracted from the input signal of each phase to extract the edge component of the input signal of each phase. An amplification circuit then multiplies the edge component of the input signal of each phase by a prescribed factor, and an addition circuit next adds this multiplied edge component to the input signal of each phase.
    Type: Application
    Filed: October 26, 2005
    Publication date: May 11, 2006
    Applicant: NEC VIEWTECHNOLOGY, LTD.
    Inventors: Michio Kobayashi, Eifu Nezu, Reiichi Kobayashi