Abstract: A signal discriminating and monitoring circuit provides a full black detection circuit which detects a full black signal input during the change of the video signal and holds the detection result of the full black signal only during the specified time period. When a full black video signal is detected in the full black detection circuit, the signal discriminating and monitoring circuit detects whether the resolution of the video signal input has changed by determining whether the frequency of the horizontal synchronization signal included in the video signal of the next frame to be input changed above a preset value. When a change in the resolution of the video signal is detected, the change detected signal indicates that the detection result is output. When a scalar circuit receives the change detected signal, the video display signal is output as a constant value in order to set the display video in the static state.

Abstract: A signal discriminating and monitoring circuit provides a full black detection circuit which detects a full black signal input during the change of the video signal and holds the detection result of the full black signal only during the specified time period. When a full black video signal is detected in the full black detection circuit, the signal discriminating and monitoring circuit detects whether the resolution of the video signal input has changed by determining whether the frequency of the horizontal synchronization signal included in the video signal of the next frame to be input changed above a preset value. When a change in the resolution of the video signal is detected, the change detected signal indicates that the detection result is output. When a scalar circuit receives the change detected signal, the video display signal is output as a constant value in order to set the display video in the static state.

Abstract: A timing signal transferring circuit (10) that may be arranged to stably transfer a timing signal (S1) between two video signal processing circuits that may operate at different clock frequencies has been disclosed. A first timing signal (S1) may be received from a pre-stage video processing circuit (13). The first timing signal (S1) may be synchronous with a pre-stage system clock (C1) and may be set to the vicinity of a center of a screen by a video signal. A second timing signal (S2) may be generated on the basis of first timing signal (S1) and transferred to a post-stage video signal processing circuit (14). Second timing signal (S2) may be synchronous with a post-stage system clock (C2). In this way, a disturbance or distortion of a video on a screen due to a difference in system clock frequency affecting a video signal in the post-stage circuit may be reduced or eliminated.

Abstract: A timing signal transferring circuit (10) that may be arranged to stably transfer a timing signal (S1) between two video signal processing circuits that may operate at different clock frequencies has been disclosed. A first timing signal (S1) may be received from a pre-stage video processing circuit (13). The first timing signal (S1) may be synchronous with a pre-stage system clock (C1) and may be set to the vicinity of a center of a screen by a video signal. A second timing signal (S2) may be generated on the basis of first timing signal (S1) and transferred to a post-stage video signal processing circuit (14). Second timing signal (S2) may be synchronous with a post-stage system clock (C2). In this way, a disturbance or distortion of a video on a screen due to a difference in system clock frequency affecting a video signal in the post-stage circuit may be reduced or eliminated.