Patents by Inventor Eiichi Kono

Eiichi Kono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070102490
    Abstract: A through hole 2 in a circuit board 1 and to be joined to a lead 5 in a surface mounting component 6 is prepared from a material such as nickel, and palladium having a thermal conductivity equal to or less than 100 W/m.K, the circuit board 1 involving a alloy layer composed of at least a member selected from elements of solder 8, a pad 7, and the lead 5 in a solder joined site of the lead 5 and the pad 7, whereby a quantity of heat transmitted to the joined site via the through hole 2 is reduced at the time when wave-soldering is applied to the back of the circuit board 1 after the surface mounting component 6 was mounted, so that the joined site is maintained at a temperature equal to or less than a melting point of the alloy layer, and hence, exfoliation in an interface of the joined site is prevented, and reliability in the joint of the lead 5 and the pad 7 is elevated.
    Type: Application
    Filed: December 19, 2006
    Publication date: May 10, 2007
    Applicant: NEC CORPORATION
    Inventors: Yuki Momokawa, Eiichi Kono, Masaru Saitou, Kazuhiko Tanabe
  • Patent number: 6940023
    Abstract: The present invention provides a board ensuring no peel-off of a wall and a land, even if a part is soldered to the board with lead-free solder. The board 10 is comprised of N (N?3) layer patterns electrically insulated from one another, and is formed with a through-hole 14 into which an electrode 19 of an electronic part 18 is to be inserted. An external land 15 is formed on a surface of each of the first and N-th layer patterns. An electrically conductive layer 17 is formed on an inner wall of the through-hole 14 such that the electrically conductive layer is electrically connected to the external land 15 of each of the first and N-th layer patterns. The electronic part 18 is fixed in the through-hole 14 with lead-free solder 20 filled in the through-hole 14. At least one internal land 16 extending from the electrically conductive layer 17 is formed in the same layer as a M-th layer pattern (2?M?(N?1)). The internal land 16 is not electrically connected to the M-th layer pattern.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: September 6, 2005
    Assignee: NEC Corporation
    Inventors: Naomi Ishizuka, Eiichi Kono
  • Publication number: 20040262040
    Abstract: The present invention provides a board ensuring no peel-off of a wall and a land, even if a part is soldered to the board with lead-free solder. The board 10 is comprised of N (N≧3) layer patterns electrically insulated from one another, and is formed with a through-hole 14 into which an electrode 19 of an electronic part 18 is to be inserted. An external land 15 is formed on a surface of each of the first and N-th layer patterns. An electrically conductive layer 17 is formed on an inner wall of the through-hole 14 such that the electrically conductive layer is electrically connected to the external land 15 of each of the first and N-th layer patterns. The electronic part 18 is fixed in the through-hole 14 with lead-free solder 20 filled in the through-hole 14. At least one internal land 16 extending from the electrically conductive layer 17 is formed in the same layer as a M-th layer pattern (2≦M≦(N-1)). The internal land 16 is not electrically connected to the M-th layer pattern.
    Type: Application
    Filed: July 16, 2004
    Publication date: December 30, 2004
    Inventors: Naomi Ishizuka, Eiichi Kono
  • Publication number: 20040238211
    Abstract: A through hole 2 in a circuit board 1 and to be joined to a lead 5 in a surface mounting component 6 is prepared from a material such as nickel, and palladium having a thermal conductivity equal to or less than 100 W/m.K, the circuit board 1 involving a alloy layer composed of at least a member selected from elements of solder 8, a pad 7, and the lead 5 in a solder joined site of the lead 5 and the pad 7, whereby a quantity of heat transmitted to the joined site via the through hole 2 is reduced at the time when wave-soldering is applied to the back of the circuit board 1 after the surface mounting component 6 was mounted, so that the joined site is maintained at a temperature equal to or less than a melting point of the alloy layer, and hence, exfoliation in an interface of the joined site is prevented, and reliability in the joint of the lead 5 and the pad 7 is elevated.
    Type: Application
    Filed: June 17, 2004
    Publication date: December 2, 2004
    Inventors: Yuki Momokawa, Eiichi Kono, Masaru Saitou, Kazuhiko Tanabe
  • Patent number: 6617529
    Abstract: In a circuit board having lands 2 each of which has a through hole 4 through which a lead of an electrical part is inserted, the lead 3 and the land 2 being mounted in the circuit board by using lead-free solder 6, the width of the land 2 corresponding to the difference in radius between the land 2 and the through hole 4 is set to about 0.40 mm or more. The width of the land 2 is set to such a value that the land exfoliation due to the solidification/shrinkage of the lead-free solder 6 and the shrinkage of the circuit board in the thickness direction can be prevented. The circuit board 1 has circuit wires at least on both the surface and the back surface.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: September 9, 2003
    Assignee: NEC Corporation
    Inventors: Naomi Ishizuka, Akihito Matsumoto, Eiichi Kono, Motoji Suzuki, Akihiro Sato, Hiroshi Matsuoka, Masafumi Kanai
  • Publication number: 20020074164
    Abstract: In a circuit board having lands 2 each of which has a through hole 4 through which a lead of an electrical part is inserted, the lead 3 and the land 2 being mounted in the circuit board by using lead-free solder 6, the width of the land 2 corresponding to the difference in radius between the land 2 and the through hole 4 is set to about 0.40 mm or more. The width of the land 2 is set to such a value that the land exfoliation due to the solidification/shrinkage of the lead-free solder 6 and the shrinkage of the circuit board in the thickness direction can be prevented. The circuit board 1 has circuit wires at least on both the surface and the back surface.
    Type: Application
    Filed: November 6, 2001
    Publication date: June 20, 2002
    Applicant: NEC CORPORATION
    Inventors: Naomi Ishizuka, Akihito Matsumoto, Eiichi Kono, Motoji Suzuki, Akihiro Sato, Hiroshi Matsuoka, Masafumi Kanai
  • Patent number: D516616
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: March 7, 2006
    Assignee: Microsoft Corporation
    Inventors: Eiichi Kono, Takeharu Suzuki
  • Patent number: D516617
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: March 7, 2006
    Assignee: Microsoft Corporation
    Inventors: Eiichi Kono, Takeharu Suzuki
  • Patent number: D518848
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: April 11, 2006
    Assignee: Microsoft Corporation
    Inventors: Eiichi Kono, Takeharu Suzuki
  • Patent number: D520555
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: May 9, 2006
    Assignee: Microsoft Corporation
    Inventors: Eiichi Kono, Takeharu Suzuki
  • Patent number: D522042
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: May 30, 2006
    Assignee: Microsoft Corporation
    Inventors: Eiichi Kono, Takeharu Suzuki
  • Patent number: D522043
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: May 30, 2006
    Assignee: Microsoft Corporation
    Inventors: Eiichi Kono, Takeharu Suzuki
  • Patent number: D536727
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: February 13, 2007
    Assignee: Microsoft Corporation
    Inventors: Matthew Carter, Eiichi Kono
  • Patent number: D540849
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: April 17, 2007
    Assignee: Microsoft Corporation
    Inventors: Matthew Carter, Eiichi Kono
  • Patent number: D540850
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: April 17, 2007
    Assignee: Microsoft Corporation
    Inventors: Matthew Carter, Eiichi Kono