Patents by Inventor Eiichi Munetsugu

Eiichi Munetsugu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5745774
    Abstract: An integrated circuit of this invention includes a processor, a first circuit for generating a clock signal, and a second circuit for selecting a suitable line voltage. The first circuit generates at least two kinds of clock signals. When one kind of clock signal having a high frequency is selected for use, the processor gives an instruction to the second circuit so as to change the connection between external batteries, and so, to obtain a high line voltage. On the contrary, when the other kind of clock signal having a low frequency is selected for use, said processor gives an instruction to the second circuit so as to change the connection between the batteries, and so, to obtain a low line voltage.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: April 28, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiichi Munetsugu
  • Patent number: 5260698
    Abstract: The pixel drive output terminals of an integrated circuit for liquid crystal display are grouped into two array-portions, one of the array-portions including odd numbered output terminals associated with the odd numbered pixels and the other of array-portions including even numbered output terminals associated with the even numbered pixels.
    Type: Grant
    Filed: June 19, 1991
    Date of Patent: November 9, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Munetsugu, Hirofumi Saita
  • Patent number: 5241304
    Abstract: A dot-matrix display apparatus comprising a display panel and two integrated circuits. The panel has a number of column electrodes extending vertically and parallel to one another, and a number of row electrodes extending horizontally and parallel to one another. Two TAB films are secured to the upper and lower edges of the panel. The integrated circuits are mounted on these TAB films, respectively. The first integrated circuit distributes odd-numbered ones of pixel data items simultaneously to the odd-numbered column electrodes, whereas the second integrated circuit distributes the even-numbered pixel data simultaneously to the even-numbered column electrodes. Either integrated circuit has an interface circuit and a control circuit, which cooperate to select the odd-numbered pixel data items or the even-numbered pixel data items. The pixel data items, thus selected, are stored into a RAM, and are supplied to the column electrodes, when necessary.
    Type: Grant
    Filed: June 8, 1990
    Date of Patent: August 31, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Munetsugu, Kiyoshi Hidaka
  • Patent number: 4587519
    Abstract: An input device in use for electronic calculators with a segment type display section of a plurality of digits comprises a key switch matrix supplied with at least some of the signals applied to the segment of the display section, a latch circuit for detecting the key operation and latching the input signal representative thereof, a control section for detecting the required operation according to the input signal from the latch circuit for performing the required operation in accordance with the input signal and for producing a display signal, and a selector gate circuit which supplies the signal containing key-in detection pulse when the key operation is not detected to the segments and the key switch matrix, and sequentially supplies the key-in judging pulse to the key switches on the column lines of the key switch matrix when the key operation is detected.
    Type: Grant
    Filed: July 13, 1982
    Date of Patent: May 6, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Eiichi Munetsugu, Hiroshi Ushiki
  • Patent number: 4571690
    Abstract: Two different set voltages are respectively compared with a power source voltage. When the smaller set voltage which is close to a minimum operating voltage of an arithmetic circuit coincides with the power source voltage, a clock signal generator, and hence the arithmetic circuit are stopped. When the power source voltage increases to coincide with the larger set voltage after the clock signal generator is stopped, the clock signal generator and hence the arithmetic circuit are restarted.
    Type: Grant
    Filed: March 29, 1983
    Date of Patent: February 18, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Eiichi Munetsugu
  • Patent number: 4519044
    Abstract: When a mode changeover switch is shifted to musical instrument mode position and a key scale assigning key is operated, symbol ".music-sharp." or "b" is displayed on a display means according to the selected key scale. Numeral keys and a decimal point key are then operated to play a wide variety of musical tones on the selected key scale.
    Type: Grant
    Filed: November 9, 1981
    Date of Patent: May 21, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Eiichi Munetsugu
  • Patent number: 4231024
    Abstract: A data-entry device for digital arithmetic processing apparatus which has a semiconductor integrated circuit provided with a plurality of terminals, key signal control leads, the one side ends of which are connected to respective ones of the plurality of terminals, and a keyboard device having terminals connected to the other side ends of the key signal control leads. The semiconductor integrated circuit includes a plurality of FET's with respective drains connected to respective terminals of the semiconductor integrated circuit with sources grounded and with gates applied with key signal-generating pulses in different timings. The semiconductor integrated circuit further includes at least one timing inhibition circuit which has a first input terminal connected to at least one of the terminals of the semiconductor integrated circuit and has a second input terminal supplied with a key signal-generating pulse.
    Type: Grant
    Filed: November 12, 1976
    Date of Patent: October 28, 1980
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Eiichi Munetsugu