Patents by Inventor Eiichiroh Kuwako
Eiichiroh Kuwako has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7521306Abstract: A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 whiType: GrantFiled: August 2, 2005Date of Patent: April 21, 2009Assignee: Sanyo Electric Co., LtdInventors: Hirotoshi Kubo, Masanao Kitagawa, Masahito Onda, Hiroaki Saito, Eiichiroh Kuwako
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Publication number: 20050266642Abstract: A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 whiType: ApplicationFiled: August 2, 2005Publication date: December 1, 2005Inventors: Hirotoshi Kubo, Masanao Kitagawa, Masahito Onda, Hiroaki Saito, Eiichiroh Kuwako
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Patent number: 6939776Abstract: A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 whiType: GrantFiled: November 19, 2001Date of Patent: September 6, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Masanao Kitagawa, Masahito Onda, Hiroaki Saito, Eiichiroh Kuwako
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Patent number: 6537899Abstract: The invention relates to a power MOSFET and reduction of the number of mask steps in a process of fabricating the power MOSFET. The increase of a parasitic capacitance due to the reduction is suppressed. In place of a thick insulating film 3, a gate insulating film 12 is formed on the entire surface of a semiconductor substrate. The gate-drain parasitic capacitance which uses the gate insulating film as a dielectric is suppressed by forming a removal region EL.Type: GrantFiled: September 15, 1998Date of Patent: March 25, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Eiichiroh Kuwako
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Patent number: 6395604Abstract: The present invention improves the characteristic of a trench-type vertical MOSFET. When a trench 23 serving as a gate 25 is formed, it is made in a shape of “&ggr;” which is convex toward the inside of the trench. Thus, the surface area of the trench is reduced so that both gate-source capacitance and gate-drain capacitance can be reduced, thereby shortening the switching time of the MOSFET.Type: GrantFiled: August 31, 2000Date of Patent: May 28, 2002Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Hiroaki Saito, Masanao Kitagawa, Eiichiroh Kuwako
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Publication number: 20020030233Abstract: A power MOSFET comprises: a semiconductor substrate 21 of a first conduction type; a drain layer 22 of the first conduction type and formed on a surface layer of the substrate; a gate insulating film 25 formed in a partial region on the drain layer 22; a gate electrode 26 formed on the gate insulating film 25; an insulating film 27 formed on the gate electrode; a side wall insulator 28 formed on side walls of the gate insulating film 25, the gate electrode 26, and the insulating film 27; a recess formed on the drain layer 22 and in a region other than a region where the gate electrode 25 and the side wall insulator 28 are formed; a channel layer 23 of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode 26 is formed; a source region layer 24 of the one conduction type and formed on the channel layer 23 outside the recess; and a wiring layer 29 formed to cover the channel layer 23 whiType: ApplicationFiled: November 19, 2001Publication date: March 14, 2002Applicant: SANYO ELECTRIC CO., LTD.Inventors: Hirotoshi Kubo, Masanao Kitagawa, Masahito Onda, Hiroaki Saito, Eiichiroh Kuwako
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Publication number: 20020008282Abstract: The invention relates to a power MOSFET and reduction of the number of mask steps in a process of fabricating the power MOSFET. The increase of a parasitic capacitance due to the reduction is suppressed. In place of a thick insulating film 3, a gate insulating film 12 is formed on the entire surface of a semiconductor substrate. The gate-drain parasitic capacitance which uses the gate insulating film as a dielectric is suppressed by forming a removal region EL.Type: ApplicationFiled: September 15, 1998Publication date: January 24, 2002Inventors: HIROTOSHI KUBO, EIICHIROH KUWAKO
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Patent number: 6137135Abstract: The present invention improves the characteristic of a trench-type vertical MOSFET. When a trench 23 serving as a gate 25 is formed, it is made in a shape of ".gamma." which is convex toward the inside of the trench. Thus, the surface area of the trench is reduced so that both gate-source capacitance and gate-drain capacitance can be reduced, thereby shortening the switching time of the MOSFET.Type: GrantFiled: August 7, 1998Date of Patent: October 24, 2000Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Hiroaki Saito, Masanao Kitagawa, Eiichiroh Kuwako
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Patent number: 5972741Abstract: A first conductivity layer and a first insulating film are successively formed on a channel layer, and a photoresist film is formed on the first insulating film. The photoresist film is selectively exposed to light using a photomask and patterned. Using the patterned photoresist film as a mask, the first insulating film and the first conductivity layer are etched to form source electrodes from the first conductivity layer. Using the first insulating film and the source electrodes as a mask, an impurity of one conductivity type is diffused into exposed portions of the channel layer to form source regions. A second insulating film is formed in covering relation to side walls and upper surfaces of the source electrodes. Using the second insulating film as a mask, the channel layer and the common drain layer are etched to form trenches in the source regions, the channel layer, and the common drain layer.Type: GrantFiled: October 28, 1997Date of Patent: October 26, 1999Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Eiichiroh Kuwako, Masanao Kitagawa, Masahito Onda, Hiroaki Saitou, Keita Odajima
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Patent number: 5970344Abstract: A channel layer is formed in a surface of a semiconductor substrate, and a plurality of trenches are formed in the surface of the semiconductor substrate, the trenches being deeper than the channel layer. Then, gate electrodes are formed in the trenches, respectively, after which body layers are formed between the trenches and source layers are formed adjacent to the trenches.Type: GrantFiled: August 24, 1998Date of Patent: October 19, 1999Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Eiichiroh Kuwako, Masanao Kitagawa, Hiroaki Saito