Patents by Inventor Eiji Hagimoto

Eiji Hagimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5969417
    Abstract: A chip package device comprises on its outside surface a plurality of wire bonding electrodes adjacent a plurality of facedown electrodes. The chip package device comprises an IC chip having a plurality of chip electrodes on its face surface and a contact sheet having an inside surface on the face surface and comprising on the outside surface a plurality of conductor patterns which comprises portions extending through the contact sheet to the chip electrodes, respectively, and defines the facedown and the wire bonding electrodes. Such chip package devices can be mounted on a printed circuit board in whichever of a facedown and a wire bonding manner when primary and secondary pads are formed on the board for mechanical and electrical connection to the facedown electrodes, respectively, and for electric connection by bonding wires to the wire bonding electrodes, respectively.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: October 19, 1999
    Assignee: NEC Corporation
    Inventors: Koji Yamashita, Yasunori Tanaka, Eiji Hagimoto
  • Patent number: 5909055
    Abstract: A chip package device comprises on its outside surface a plurality of wire bonding electrodes adjacent a plurality of facedown electrodes. The chip package device comprises an IC chip having a plurality of chip electrodes on its face surface and a contact sheet having an inside surface on the face surface and comprising on the outside surface a plurality of conductor patterns which comprises portions extending through the contact sheet to the chip electrodes, respectively, and defines the facedown and the wire bonding electrodes. Such chip package devices can be mounted on a printed circuit board in whichever of a facedown and a wire bonding manner when primary and secondary pads are formed on the board for mechanical and electrical connection to the facedown electrodes, respectively, and for electric connection by bonding wires to the wire bonding electrodes, respectively.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: June 1, 1999
    Assignee: NEC Corporation
    Inventors: Koji Yamashita, Yasunori Tanaka, Eiji Hagimoto
  • Patent number: 5905303
    Abstract: An insulating film has conductive layers on a first surface and conductive protrusions on a second surface. The conductive layers are connected to the conductive protrusions via through holes provided in the insulating film. A semiconductor chip having pads is adhered by an adhesive layer to the insulating film. Then, the conductive layers are locally pressured, so that the conductive layers are electrically connected to respective ones of the pads.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: May 18, 1999
    Assignee: NEC Corporation
    Inventors: Keiichiro Kata, Shuichi Matsuda, Eiji Hagimoto
  • Patent number: 5683942
    Abstract: An insulating film has conductive layers on a first surface and conductive protrusions on a second surface. The conductive layers are connected to the conductive protrusions via through holes provided in the insulating film. A semiconductor chip having pads is adhered by an adhesive layer to the insulating film. Then, the conductive layers are locally pressured, so that the conductive layers are electrically connected to respective ones of the pads.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: November 4, 1997
    Assignee: NEC Corporation
    Inventors: Keiichiro Kata, Shuichi Matsuda, Eiji Hagimoto