Abstract: Provided is an exhaust gas purification system that allows suppressing the emission of carbon monoxide (CO). An exhaust gas purification system includes a three-way catalyst and a particulate filter and a control device. The three-way catalyst and the particulate filter are arranged respectively on an upstream side and a downstream side of an exhaust channel connected to an internal combustion engine. The control device controls the internal combustion engine so as to execute fuel cut during a deceleration operation of the internal combustion engine. The particulate filter includes a honeycomb substrate and an outflow cell side catalyst layer. The honeycomb substrate includes a porous partition wall defining a plurality of cells extending from an inflow side end surface to an outflow side end surface. The plurality of cells include an inflow cell and an outflow cell adjacent across the partition wall. The inflow cell has an open inflow side end and a sealed outflow side end.

Abstract: This invention is intended to insert test points in a logic circuit under test in an effective manner. The logic circuit testing apparatus includes a fault estimation unit that estimates fault likelihoods for each of signal lines in a logic circuit in accordance with wiring conditions obtained from design data for the logic circuit. The logic circuit testing apparatus also includes an insertion unit that inserts test points, based on the fault likelihoods. The logic circuit testing apparatus executes testing the logic circuit in which the test points were inserted by the insertion unit.

Abstract: Provided is a test apparatus for testing a specimen by using a test pattern and an expected value pattern. The test apparatus includes: a control unit for outputting a test pattern to the specimen; a pattern converting unit for converting the expected value pattern based on an output pattern output from the specimen upon an input of the test pattern; and a determination unit for determining the specimen as a non-defective product or a defective product by using the converted expected value pattern.

Abstract: A burn-in test circuit according to the present invention includes a scan chain formed by a plurality of scan flip-flips connected in series, a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal, and a scan chain loop circuit being configured to an output signal of the scan chain determined according to an output of the circuit under test back to the scan chain.

Abstract: According to an embodiment of the invention, a semiconductor testing system for testing a semiconductor device including an output buffer switching between a first mode for outputting data based on an input test signal and a second mode for setting an output terminal to a high impedance state, includes: a test signal generator supplying the test signal to the semiconductor device; an external tester setting an output terminal of the output buffer to a predetermined potential if the output buffer is set to the second mode; and a detecting circuit measuring a potential of an output of the output buffer, the detecting circuit detecting a stuck-at fault in the semiconductor device based on the data if the test signal designates the first mode and detecting a stuck-at fault in the semiconductor device based on the predetermined potential if the test signal designates the second mode.

Abstract: Provided is a test apparatus for testing a specimen by using a test pattern and an expected value pattern. The test apparatus includes: a control unit for outputting a test pattern to the specimen; a pattern converting unit for converting the expected value pattern based on an output pattern output from the specimen upon an input of the test pattern; and a determination unit for determining the specimen as a non-defective product or a defective product by using the converted expected value pattern.

Abstract: The invention provides an overload detector with a simplified system configuration to be applied to a railway car having a connecting bogie. A connecting bogie 52 (two axle bogie) having front and rear wheels 52C and 52D are disposed to extend between a first car C1 and a second car C2. The front and rear cars C1 and C2 are supported via air springs 52A and 52B on the connecting bogie 52. The other end of the car C1 is supported via air springs 51A and 51B on a bogie 51 (two axle bogie) having front and rear wheels 51C and 51D. The other end of the car C2 is supported via air springs 53A and 53B on a bogie 53 (two axle bogie) having front and rear wheels 53C and 53D. Pneumoelectric converters 41 and 42 are disposed along paths of pneumatic pipings 21 and 22, and the inner pressure of air springs 51A and 51B is converted into an inner pressure signal AS1, and the inner pressure PAS2 of the air springs 52A and 52B is converted into an inner pressure signal AS2.

Abstract: A vehicular back trim of the present invention includes a bulge formed in the middle of the vehicle width and between right and left seats to protrude more forward than the rear surfaces of seatbacks of the seats. A center container is formed to extend rearward from the front side of the bulge and behind-seatback containers are formed to extend rearward from the surface located behind the seatbacks of the seats.

Abstract: According to an embodiment of the invention, a semiconductor testing system for testing a semiconductor device including an output buffer switching between a first mode for outputting data based on an input test signal and a second mode for setting an output terminal to a high impedance state, includes: a test signal generator supplying the test signal to the semiconductor device; an external tester setting an output terminal of the output buffer to a predetermined potential if the output buffer is set to the second mode; and a detecting circuit measuring a potential of an output of the output buffer, the detecting circuit detecting a stuck-at fault in the semiconductor device based on the data if the test signal designates the first mode and detecting a stuck-at fault in the semiconductor device based on the predetermined potential if the test signal designates the second mode.

Abstract: A burn-in test circuit according to the present invention includes a scan chain formed by a plurality of scan flip-flips connected in series, a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal, and a scan chain loop circuit being configured to an output signal of the scan chain determined according to an output of the circuit under test back to the scan chain.

Abstract: The invention provides an overload detector with a simplified system configuration to be applied to a railway car having a connecting bogie. A connecting bogie 52 (two axle bogie) having front and rear wheels 52C and 52D are disposed to extend between a first car C1 and a second car C2. The front and rear cars C1 and C2 are supported via air springs 52A and 52B on the connecting bogie 52. The other end of the car C1 is supported via air springs 51A and 51B on a bogie 51 (two axle bogie) having front and rear wheels 51C and 51D. The other end of the car C2 is supported via air springs 53A and 53B on a bogie 53 (two axle bogie) having front and rear wheels 53C and 53D. Pneumoelectric converters 41 and 42 are disposed along paths of pneumatic pipings 21 and 22, and the inner pressure of air springs 51A and 51B is converted into an inner pressure signal AS1, and the inner pressure PAS2 of the air springs 52A and 52B is converted into an inner pressure signal AS2.

Abstract: A vehicular back trim of the present invention includes a bulge formed in the middle of the vehicle width and between right and left seats to protrude more forward than the rear surfaces of seatbacks of the seats. A center container is formed to extend rearward from the front side of the bulge and behind-seatback containers are formed to extend rearward from the surface located behind the seatbacks of the seats.

Abstract: A fault simulation method for simulating an entire circuit represented by a gate model, comprises the steps of preparing a plurality of fault circuits represented by gate models, which are equal in number to the number of internal faults, with the internal faults assumed in the entire circuit, of dividing each of the fault circuits into a plurality of partial circuits each of which is represented by the gate model, of replacing internal faults in the partial circuits with external faults out of the partial circuits that are equivalent to the internal faults; of translating the partial circuits into translated partial circuits represented by superior models which have operation speed faster than that of the gate models, and of simultaneously simulating both of a good circuit represented by the superior model and the fault circuits represented by the superior models to determine whether or not the internal faults can be detected by comparing results of simulations.

Abstract: An automatic programming system automatically decides which machining system should perform which machining step and generates a machining program therefor. The programming system utilizes a machining step information, a workpiece information, a tool information and a machining step corresponding workpiece information. The machining step information defines a machining step kind and a machining specification for each machining step. The workpiece information defines a workpiece material and a workpiece shape for each workpiece. The tool information defines a specification of a tool used in each machining system, a machining step kind workable and workpiece material workable by the tool. The machining step corresponding workpiece information defines a workpiece used in each machining step.

Abstract: A semiconductor device is disclosed in which at least two semiconductor elements each having a self turn-off function are disposed in a package and connected in paralllel, and in which the semiconductor elements, terminals mounted on the package, and internal wirings for connecting the semiconductor elements to the terminals are arranged in geometrical symmetry, to eliminate the imbalance of current between the semiconductor elements.