Patents by Inventor Eiji I. Nakamura
Eiji I. Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10741514Abstract: Wafers include a contact pad on a surface of a bulk redistribution layer. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.Type: GrantFiled: November 6, 2019Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Patent number: 10692829Abstract: A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.Type: GrantFiled: October 25, 2019Date of Patent: June 23, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Patent number: 10607956Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.Type: GrantFiled: November 3, 2017Date of Patent: March 31, 2020Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Patent number: 10593616Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.Type: GrantFiled: December 21, 2017Date of Patent: March 17, 2020Assignee: Tessera, Inc.Inventors: Toyohiro Aoki, Takashi Hisada, Akihiro Horibe, Sayuri Hada, Eiji I. Nakamura, Kuniaki Sueoka
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Publication number: 20200075522Abstract: Wafers include a contact pad on a surface of a bulk redistribution layer. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Publication number: 20200058612Abstract: A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.Type: ApplicationFiled: October 25, 2019Publication date: February 20, 2020Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Patent number: 10566302Abstract: Wafers include multiple bulk redistribution layers. A contact pad is formed on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.Type: GrantFiled: May 23, 2018Date of Patent: February 18, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Patent number: 10553553Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.Type: GrantFiled: July 26, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Publication number: 20190214339Abstract: Methods for fabricating a via structure are disclosed. In one method, fabricating the via structure includes disposing a stress buffer layer on a first surface of a substrate. The stress buffer layer has an opening aligned to a via hole of the substrate. The method further includes filling the via hole with a conductive material at least up to the first surface of the substrate. The stress buffer layer reduces stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate, and the conductive material extends into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface of the substrate around the via hole.Type: ApplicationFiled: March 14, 2019Publication date: July 11, 2019Inventors: Toyohiro Aoki, Takashi Hisada, Akihiro Horibe, Sayuri Hada, Eiji I. Nakamura, Kuniaki Sueoka
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Patent number: 10325839Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.Type: GrantFiled: April 6, 2017Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Takashi Hisada, Akihiro Horibe, Sayuri Hada, Eiji I. Nakamura, Kuniaki Sueoka
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Patent number: 10103118Abstract: Wafers and methods of forming solder balls include etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal contact pad. Solder is injected into the hole using an injection nozzle that is in direct contact with the final redistribution layer. The final redistribution layer is etched back. The injected solder is reflowed to form a solder ball.Type: GrantFiled: October 2, 2017Date of Patent: October 16, 2018Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Takashi Hisada, Eiji I Nakamura
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Publication number: 20180294213Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.Type: ApplicationFiled: April 6, 2017Publication date: October 11, 2018Inventors: Toyohiro Aoki, Takashi Hisada, Akihiro Horibe, Sayuri Hada, Eiji I. Nakamura, Kuniaki Sueoka
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Publication number: 20180294214Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.Type: ApplicationFiled: December 21, 2017Publication date: October 11, 2018Inventors: Toyohiro Aoki, Takashi Hisada, Akihiro Horibe, Sayuri Hada, Eiji I. Nakamura, Kuniaki Sueoka
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Publication number: 20180269173Abstract: Wafers include multiple bulk redistribution layers. A contact pad is formed on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.Type: ApplicationFiled: May 23, 2018Publication date: September 20, 2018Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Patent number: 10037958Abstract: Wafers include multiple bulk redistribution layers. A terminal contact pad is on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the terminal contact pad. The final redistribution layer is formed from a material other than a material of the plurality of bulk redistribution layers. A solder ball is formed on the terminal contact pad.Type: GrantFiled: June 16, 2017Date of Patent: July 31, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Publication number: 20180061797Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.Type: ApplicationFiled: November 3, 2017Publication date: March 1, 2018Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Publication number: 20180061796Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.Type: ApplicationFiled: July 26, 2017Publication date: March 1, 2018Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
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Patent number: 9859241Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.Type: GrantFiled: September 1, 2016Date of Patent: January 2, 2018Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Takashi Hisada, Eiji I Nakamura
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Patent number: 9837367Abstract: Wafers and methods of forming solder balls include forming a final redistribution layer over terminal contact pad on a surface of a wafer. The wafer includes multiple bulk redistribution layers. A hole is etched in the final redistribution layer to expose the terminal contact pad. Solder is injected into the hole using an injection nozzle that is in direct contact with the final redistribution layer. The final redistribution layer is etched back. The injected solder is reflowed to form a solder ball.Type: GrantFiled: October 19, 2016Date of Patent: December 5, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura