Patents by Inventor Eiji Iwata
Eiji Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11976851Abstract: A refrigeration cycle device that includes a main refrigerant circuit and a sub-refrigerant circuit cools or heats a main refrigerant that flows between a main heat-source-side heat exchanger and a main usage-side heat exchanger by causing a sub-usage-side heat exchanger to function as an evaporator or a radiator of a sub-refrigerant. A first main expansion mechanism and a second main expansion mechanism that decompress the main refrigerant are provided on an upstream side and a downstream side of the sub-usage-side heat exchanger of the main refrigerant circuit.Type: GrantFiled: September 30, 2019Date of Patent: May 7, 2024Assignee: DAIKIN INDUSTRIES, LTD.Inventors: Ikuhiro Iwata, Eiji Kumakura, Kazuhiro Furusho, Ryusuke Fujiyoshi, Hiromune Matsuoka
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Patent number: 11959667Abstract: A suction injection pipe and a subcooling heat exchanger are provided at a main refrigerant circuit in which a main refrigerant circulates. Further, a sub-refrigerant circuit that differs from the main refrigerant circuit and in which a sub-refrigerant circulates is provided. A controller performs control for switching between a cooling action of the subcooling heat-exchanger that cools the main refrigerant that is sent to a main use-side heat exchanger by using the suction injection pipe and the subcooling heat exchanger, and a cooling action of the sub-refrigerant-circuit that cools the main refrigerant that is sent to the main use-side heat exchanger by using the sub-refrigerant circuit.Type: GrantFiled: September 27, 2019Date of Patent: April 16, 2024Assignee: Daikin Industries, Ltd.Inventors: Ikuhiro Iwata, Eiji Kumakura, Kazuhiro Furusho, Ryusuke Fujiyoshi, Hiromune Matsuoka
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Patent number: 11738270Abstract: A simulation system including a processor, the processor performs an information acquisition process acquiring real space information obtainable by a recognition process of a real space and user information; a virtual space generation process generating a virtual space corresponding to the real space based on the real space information; an object process that sets a reference point in the virtual space based on the user information and the real space information, and disposes an object of a character in the virtual space based on the reference point; and a display process displaying an image including an image of the character. The object process sets a hit volume based on a position of a user moving body in the virtual space, and performs a process with respect to the character in accordance with a positional relationship between the hit volume and the character when the user performs a given input.Type: GrantFiled: August 7, 2020Date of Patent: August 29, 2023Assignee: BANDAI NAMCO Entertainment Inc.Inventors: Eiji Iwata, Nobuyuki Morishima
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Publication number: 20200368625Abstract: A simulation system including a processor, the processor performs an information acquisition process acquiring real space information obtainable by a recognition process of a real space and user information; a virtual space generation process generating a virtual space corresponding to the real space based on the real space information; an object process that sets a reference point in the virtual space based on the user information and the real space information, and disposes an object of a character in the virtual space based on the reference point; and a display process displaying an image including an image of the character. The object process sets a hit volume based on a position of a user moving body in the virtual space, and performs a process with respect to the character in accordance with a positional relationship between the hit volume and the character when the user performs a given input.Type: ApplicationFiled: August 7, 2020Publication date: November 26, 2020Inventors: Eiji IWATA, Nobuyuki MORISHIMA
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Patent number: 8786796Abstract: In a structure for holding a display panel disposed within a cabinet, which includes a frame part positioned on one side of a display face of the display panel; a peripheral part positioned around the display panel; and a rear part covering the other face side of the display panel, from both sides by the frame part and a holding member supported by the peripheral part, a projecting portion projects on an inner face portion of the frame part in a position on an outer peripheral side of a rim portion of the display panel and the holding member so as to extend from the side of the display face of the display panel toward the opposite side of the display face, and a reinforcing portion for coupling the inner face portion of the projecting portion and the inner face portion of the frame part is provided.Type: GrantFiled: October 27, 2008Date of Patent: July 22, 2014Assignee: Sharp Kabushiki KaishaInventors: Keita Ito, Eiji Iwata, Masahiro Ohtake
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Publication number: 20120327307Abstract: Provided are: a light guide plate apparatus including a plurality of light guide plates arranged in parallel in which the middle part in the longitudinal direction of the light guide plates is held by a support body without blocking light diffusion in the inside of each light guide plate; a light source apparatus employing this light guide plate apparatus; a display apparatus in which the luminance distribution is homogenized in the center part of the screen; and a television receiver apparatus employing this display apparatus. A plurality of light guide plates 42 having an approximately rectangular shape and emitting light having entered through the side surface on one shorter side are supported by a support body 41, in plural lines such that the side surfaces on the longer side are facing each other.Type: ApplicationFiled: February 24, 2011Publication date: December 27, 2012Inventors: Shinichi Nakamura, Takaharu Kikuchi, Hideto Takeuchi, Eiji Iwata
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Publication number: 20120047355Abstract: An information processing apparatus operates data stored in an input register for each bit and stores a result thereof in an output register. A selector circuit selects output data of a bit from input data of 128 bits in the input register. An AND circuit outputs, only when data from a corresponding selector circuit is valid, the data to a corresponding bit of the output register. A control signal generator inputs a select signal indicating the number of a bit to be selected to each selector circuit, and also inputs a signal indicating whether data input from the selector circuit is valid or invalid to each AND circuit.Type: ApplicationFiled: July 25, 2011Publication date: February 23, 2012Applicants: Sony Computer Entertainment Inc., Sony CorporationInventors: Eiji Iwata, Ryohei Okada
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Patent number: 8001294Abstract: The present invention provides methods and apparatus for transferring and storing data among processors and memory in a multiprocessor system. The data is compressed locally before it is sent to a shared memory. The memory stores the data in its compressed state, but the data is aligned in the memory in the same manner as uncompressed data would be. A tag table keeps track of the compression type and compressed data size for a set of data at a given address block. A data compressor and a data expander may be implemented in a direct memory access controller accessible to multiple coprocessors, or the compressor and the expander may be implemented within the coprocessors.Type: GrantFiled: September 27, 2005Date of Patent: August 16, 2011Assignee: Sony Computer Entertainment Inc.Inventors: Keisuke Inoue, Eiji Iwata
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Publication number: 20100253874Abstract: In a structure for holding a display panel disposed within a cabinet, which includes a frame part positioned on one side of a display face of the display panel; a peripheral part positioned around the display panel; and a rear part covering the other face side of the display panel, from both sides by the frame part and a holding member supported by the peripheral part, a projecting portion projects on an inner face portion of the frame part in a position on an outer peripheral side of a rim portion of the display panel and the holding member so as to extend from the side of the display face of the display panel toward the opposite side of the display face, and a reinforcing portion for coupling the inner face portion of the projecting portion and the inner face portion of the frame part is provided.Type: ApplicationFiled: October 27, 2008Publication date: October 7, 2010Inventors: Keita Ito, Eiji Iwata, Masahiro Ohtake
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Publication number: 20090066706Abstract: The present multi-processor system performs information processing suitably. The system can receive, reproduce and record a variety of image contents. By comprising a powerful CPU in the multi-processors, a plurality of pieces of large image data, such as high definition image data or the like, can be processed simultaneously in parallel, which was difficult conventionally. Since task processing, such as demodulation processing or the like, is assigned respectively in view of the remaining processing capacity of each of the plurality of processors, the system can reproduce contents efficiently. By sharing roles, a plurality of different contents, such as an image, a voice, or the like can be processed simultaneously and can be displayed or reproduced at a desired timing.Type: ApplicationFiled: April 6, 2006Publication date: March 12, 2009Applicant: SONY COMPUTER ENTERTAINMENT INC.Inventors: Masahiro Yasue, Eiji Iwata, Munetaka Tsuda, Ryuji Yamamoto, Shigeru Enomoto, Hiroyuki Nagai
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Bit manipulation on data in a bitstream that is stored in a memory having an address boundary length
Patent number: 7334116Abstract: A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a bit length which is preferably greater than the address boundaries in a memory or register address. A bitstream can be processed using the buffer by itself or in combination with a standard register, depending upon the particular function to be implemented.Type: GrantFiled: October 6, 2004Date of Patent: February 19, 2008Assignee: Sony Computer Entertainment Inc.Inventor: Eiji Iwata -
Patent number: 7304646Abstract: A method is provided for transferring data for processing of an image between a first memory and a second memory accessible by a processor. According to such method, data is provided in the first memory for processing of the image, the data being organized into a plurality of blocks, wherein each block relates to a portion of the image. At least some of the data is transferred by a direct memory access controller in units of a block between the first memory and a second memory accessible by the processor.Type: GrantFiled: August 19, 2004Date of Patent: December 4, 2007Assignee: Sony Computer Entertainment Inc.Inventor: Eiji Iwata
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Publication number: 20070113612Abstract: To provide the manufacturing method for the press work product reducing the chance of causing distortion of the countersink as press-forming the countersink. This is the manufacturing method for a press work product which has a tapped bore for a stem of a flat countersink head screw to penetrate therethrough and a countersink formed around a circumferential line of the tapped bore for a head of the flat countersink head screw to seat therein, comprising steps of forming a work as the press work product by punching a plate material, trimming an outside diameter of said work, and forming said countersink by inserting said work after trimming the outside diameter into a press die to press form thereof.Type: ApplicationFiled: November 22, 2005Publication date: May 24, 2007Applicant: Kato Seisakusyo Co., Ltd.Inventors: Hideo Takekoshi, Eiji Iwata
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Publication number: 20060101246Abstract: A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a bit length which is preferably greater than the address boundaries in a memory or register address. A bitstream can be processed using the buffer by itself or in combination with a standard register, depending upon the particular function to be implemented.Type: ApplicationFiled: October 6, 2004Publication date: May 11, 2006Inventor: Eiji Iwata
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Patent number: 7038676Abstract: A system and method for compressing video graphics data are provided. The system and method include generating in a graphics pipeline, from video graphics data modeling objects, vertex data corresponding to the objects, rendering the video graphics data to produce a current frame of pixel data and a reference frame of pixel data, and, based upon the vertex data, defining a search area within the reference frame for calculating a motion vector for a block of pixel data within the current frame. The current frame then is compressed using the motion vector. The use of vertex data from the graphics pipeline to define the search area substantially reduces the amount of searching necessary to generate motion vectors and perform data compression.Type: GrantFiled: June 11, 2002Date of Patent: May 2, 2006Assignee: Sony Computer Entertainmant Inc.Inventors: Eiji Iwata, Masakazu Suzuoki
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Publication number: 20060069879Abstract: The present invention provides methods and apparatus for transferring and storing data among processors and memory in a multiprocessor system. The data is compressed locally before it is sent to a shared memory. The memory stores the data in its compressed state, but the data is aligned in the memory in the same manner as uncompressed data would be. A tag table keeps track of the compression type and compressed data size for a set of data at a given address block. A data compressor and a data expander may be implemented in a direct memory access controller accessible to multiple coprocessors, or the compressor and the expander may be implemented within the coprocessors.Type: ApplicationFiled: September 27, 2005Publication date: March 30, 2006Applicant: Sony Computer Entertainment Inc.Inventors: Keisuke Inoue, Eiji Iwata
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Publication number: 20060038821Abstract: A method is provided for transferring data for processing of an image between a first memory and a second memory accessible by a processor. According to such method, data is provided in the first memory for processing of the image, the data being organized into a plurality of blocks, wherein each block relates to a portion of the image. At least some of the data is transferred by a direct memory access controller in units of a block between the first memory and a second memory accessible by the processor.Type: ApplicationFiled: August 19, 2004Publication date: February 23, 2006Applicant: Sony Computer Entertainment Inc.Inventor: Eiji Iwata
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Publication number: 20050284203Abstract: A rolled steel plate as a raw material is press-formed into a pressed work provided with a boss section, and the work is fitted to a shaft by press-fitting of the shaft into the boss section. Rolling flow of internal metallographic layers in the boss section is curved like a letter S. Moreover, a manufacturing method of such a pressed work comprises: a primary-boss forming process during which a primary boss having a hole section and a protruding section protruding from the periphery of the hole section at a position corresponding to the boss section on a plane-like raw material is formed; and a boss-section forming process during which the protruding section is pressed and deformed in the protruding length direction to form the boss section.Type: ApplicationFiled: June 10, 2005Publication date: December 29, 2005Applicant: Kato Seisakusho Co., Ltd.Inventors: Hideo Takekoshi, Eiji Iwata
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Publication number: 20050147174Abstract: Encoding and decoding systems for MPEG encoding and decoding at a high speed using a parallel processing system, wherein macroblocks to be processed are designated for first to third processors which are made to carry out all processings of encoding, variable length coding, and local decoding of those macroblocks; the variable length coding is carried out after confirming that the variable length coding with respect to the previous macroblock is ended; the variable length coding which was normally sequentially carried out at a specific processor is carried out at all of the processors; and the encoding and local decoding are carried out at all of the processors; whereby the loads are dispersed, the efficiency is improved as a whole, and the processing speed becomes fast.Type: ApplicationFiled: February 7, 2005Publication date: July 7, 2005Inventor: Eiji Iwata
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Patent number: 6870883Abstract: Encoding and decoding systems for MPEG encoding and decoding at a high speed using a parallel processing system, wherein macroblocks to be processed are designated for first to third processors which are made to carry out all processings of encoding, variable length coding, and local decoding of those macroblocks; the variable length coding is carried out after confirming that the variable length coding with respect to the previous macroblock is ended; the variable length coding which was normally sequentially carried out at a specific processor is carried out at all of the processors; and the encoding and local decoding are carried out at all of the processors; whereby the loads are dispersed, the efficiency is improved as a whole, and the processing speed becomes fast.Type: GrantFiled: July 12, 1999Date of Patent: March 22, 2005Assignee: Sony CorporationInventor: Eiji Iwata