Abstract: A USB circuit that can prevent phase difference between a signal pair with high precision without the need for strict design conditions. In a preferred embodiment of this USB circuit, the USB controller thereof comprises a flip-flop pair to match the timings of a signal pair output to an output signal line pair and a flip-flop pair to match the timings of a signal pair input from an input signal line pair, and the USB driver thereof comprises a third flip-flop pair to match the timings of a signal pair input from the output signal line pair, and a fourth flip-flop pair to match the timings of a signal pair output to the input signal line pair.

Abstract: A memory bus arbitrating circuit selects the request signal with the highest priority when a plurality of types of request signals are inputted simultaneously. A memory controlling circuit executes memory control responsive to selection by the memory bus arbitrating circuit. A monitoring circuit outputs a refresh request signal when the count value of a refresh counter reaches a comparison value stored in an overwrite-capable memory. The count value is selectable so that refresh can be executed at a timing when other high priority processing based on the request signals is not executed. After refresh, the count value of the refresh counter is reset.

Abstract: A USB circuit that can prevent phase difference between a signal pair with high precision without the need for strict design conditions. In a preferred embodiment of this USB circuit, the USB controller thereof comprises a flip-flop pair to match the timings of a signal pair output to an output signal line pair and a flip-flop pair to match the timings of a signal pair input from an input signal line pair, and the USB driver thereof comprises a third flip-flop pair to match the timings of a signal pair input from the output signal line pair, and a fourth flip-flop pair to match the timings of a signal pair output to the input signal line pair.

Abstract: A memory bus arbitrating circuit selects the request signal with the highest priority when a plurality of types of same are inputted simultaneously. A memory controlling circuit executes relative to memory control of memory bus arbitrating circuit-selected processing. A first monitoring circuit outputs a first refresh request signal when the count value of a refresh counter reaches a first prescribed value. A second monitoring circuit outputs a second refresh request signal when the count value of a refresh counter reaches a second prescribed value, which is, for example, ½ of the first prescribed value. The first, second refresh request signals are inputted to the memory bus arbitrating circuit. The memory bus arbitrating circuit regards the first refresh request signal as the request signal with the highest priority, and regards the second refresh request signal as the request signal with the lowest priority.

Abstract: A memory bus arbitrating circuit selects the request signal with the highest priority when a plurality of types of same are inputted simultaneously. A memory controlling circuit executes relative to memory control of memory bus arbitrating circuit-selected processing. A first monitoring circuit outputs a first refresh request signal when the count value of a refresh counter reaches a first prescribed value. A second monitoring circuit outputs a second refresh request signal when the count value of a refresh counter reaches a second prescribed value, which is, for example, ½ of the first prescribed value. The first, second refresh request signals are inputted to the memory bus arbitrating circuit. The memory bus arbitrating circuit regards the first refresh request signal as the request signal with the highest priority, and regards the second refresh request signal as the request signal with the lowest priority.

Abstract: A clock signal switching circuit that switches between two clock signals having a phase difference. The clock signal switching circuit includes a first selector that selects one of the clock signals according to the level of a selection signal, a second selector that selects one of first and second control signals according to the level of the selection signal. The level of the first and second control signals are changed in response to an original signal and the first or the second clock signal. A gate circuit generates the output signal from the first and second selectors wherein the level of the selection signal is changed in response to the original signal after the levels of both of the first and second control signals have changed.

Abstract: A memory bus arbitrating circuit selects the request signal with the highest priority when a plurality of types of same are inputted simultaneously. A memory controlling circuit executes relative to memory control of memory bus arbitrating circuit-selected processing. A first monitoring circuit outputs a first refresh request signal when the count value of a refresh counter reaches a first prescribed value. A second monitoring circuit outputs a second refresh request signal when the count value of a refresh counter reaches a second prescribed value, which is, for example, ½ of the first prescribed value. The first, second refresh request signals are inputted to the memory bus arbitrating circuit. The memory bus arbitrating circuit regards the first refresh request signal as the request signal with the highest priority, and regards the second refresh request signal as the request signal with the lowest priority.

Abstract: A memory bus arbitrating circuit selects the request signal with the highest priority when a plurality of types of same are inputted simultaneously. A memory controlling circuit executes relative to memory control of memory bus arbitrating circuit-selected processing. A first monitoring circuit outputs a first refresh request signal when the count value of a refresh counter reaches a first prescribed value. A second monitoring circuit outputs a second refresh request signal when the count value of a refresh counter reaches a second prescribed value, which is, for example, ½ of the first prescribed value. The first, second refresh request signals are inputted to the memory bus arbitrating circuit. The memory bus arbitrating circuit regards the first refresh request signal as the request signal with the highest priority, and regards the second refresh request signal as the request signal with the lowest priority.

Abstract: A clock signal switching circuit that switches between two clock signals having a phase difference. The clock signal switching circuit includes a first selector that selects one of the clock signals according to the level of a selection signal, a second selector that selects one of first and second control signals according to the level of the selection signal. The level of the first and second control signals are changed in response to an original signal and the first or the second clock signal. A gate circuit generates the output signal from the first and second selectors wherein the level of the selection signal is changed in response to the original signal after the levels of both of the first and second control signals have changed.

Abstract: The first-in first-out storage device has a write counter for counting as a write address the number of data write operations of a write side circuit, a read counter for counting as a read address a number of data read operations of a read side circuit, a RAM which stores data input from the write side circuit into a storage region that corresponds to the write address when the write side circuit has performed the write operation and outputs the data stored in the storage region that corresponds to the read address to the read side circuit when the read side circuit has performed the read operation, a full-state detection unit which detects whether the write operation of the write side circuit needs to be restricted or not based on the write address and read address, a flip-flop which outputs a detection result obtained by the full-state detection unit to the write side circuit in synchronization with a write clock signal based on which the write side circuit operates, an empty-state detection unit which dete

Abstract: The present invention relates to a variable-length code decoding circuit for decoding an input variable-length code string and a variable-length code decoding system using the same. A typical variable-length code decoding circuit of the present invention includes a CAM cell 10 for storing a variable-length code bit and a RAM cell 20 which is paired with the CAM cell 10 for storing a mask bit so as to perform a masking operation. The variable-length code decoding circuit further includes an NMOS transistor 30 which is coupled between the CAM cell 10 and a match line ML for selectively disconnecting the CAM cell 10 from the match line ML in response to an output of the RAM cell 20. The CAM cell 10 collates a bit of the input variables-length code string with the stored code bit. When the input bit matches the stored code bit, the CAM cell 10 outputs an H level matching to the match line ML and otherwise it outputs an L level unmatching to the match line ML.

Abstract: A quantizing and dequantizing circuit has a first memory circuit with integer addresses, in which reciprocal data are stored, and a second memory circuit, in which a quantization table of integers is stored. The Integers stored in the second memory circuit are provided to the first memory circuit as address signals, causing output of the corresponding reciprocal data. Data to be quantized are multiplied by the reciprocal data output by the first memory circuit. Data to be dequantized are multiplied by the integers output from the second memory circuit.

Abstract: A cache memory device stores image data which are arranged corresponding to address data having first and second two-dimensional coordinate data. The image data are divided into a plurality of first groups in accordance with the first two-dimensional coordinate data, with the first groups further divided into a plurality of second groups in accordance with the second two-dimensional coordinate data. The cache memory device includes an image data memory for storing a given image data therein, which is divided into a plurality of block areas arranged in two dimensions. The reading and writing of image data from and to the image data memory is controlled by a central processing unit. A cache storage, comprising a cache memory, an address data decoding circuit, an address matching circuit and a control circuit, is coupled between the image data memory and the central processing unit by way of buses.

Abstract: A processing unit has a first data bus and a second data bus that receive first and second data from, respectively, first and second registers in a register file. An arithmetic-logic unit performs arithmetic and logic operations on the first and second data to produce third data, which it places on a third data bus. A selection circuit coupled to the first and third data buses selects either the first or third data for input to a third register in the register file, and either the first or third data for input to a fourth register in the register file. The first, second, third, and fourth registers are selected by a control circuit.