Patents by Inventor Eiji Muramoto

Eiji Muramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006561
    Abstract: A shortest distance between a first p-side electrode and a second p-side connection portion is greater than a shortest distance between the first p-side electrode and a closest one of first n-side connection portions most proximate to the first p-side electrode among a plurality of first n-side connection portions in the plan view. The second p-side electrode is located at least in a region between the first p-side electrode and the closest one of the first n-side connection portions in the plan view.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 4, 2024
    Inventors: Eiji MURAMOTO, Kosuke YOSHIOKA
  • Patent number: 11777051
    Abstract: A method of manufacturing a light-emitting element includes: providing a semiconductor structure including: a first layer containing gallium and nitrogen, a second layer of a first conductive type, the second layer containing gallium, aluminum, and nitrogen and being located on or above the first layer, an active layer located on or above the second layer, and a third layer of a second conductive type, the third layer located on or above the active layer, wherein a thickness of the first layer is larger than a thickness of the second layer; performing chemical-mechanical polishing from a first layer side to reduce the thickness of the first layer; and performing dry etching from the first layer side to remove the first layer and reduce the thickness of the second layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: October 3, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Eiji Muramoto, Maki Fujimoto
  • Publication number: 20230246138
    Abstract: A light emitting element includes: a semiconductor structure including an n-side layer, a p-side layer, and an active layer, each being made of a nitride semiconductor, wherein the active layer is positioned between the n-side layer and the p-side layer and is configured to emit ultraviolet light; an n-electrode electrically connected to the n-side layer; and a p-electrode comprising a first metal layer in contact with the p-side layer and electrically connected to the p-side layer. The p-side layer comprises a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, each containing a p-type impurity. A surface of the second layer includes an exposed region that is exposed from the third layer. The first layer and the second layer contain Al.
    Type: Application
    Filed: January 25, 2023
    Publication date: August 3, 2023
    Applicant: NICHIA CORPORATION
    Inventors: Eiji MURAMOTO, Takumi OTSUKA, Yuya YAMAKAMI, Haruhiko NISHIKAGE, Shota KAMMOTO, Akinori KISHI
  • Publication number: 20220199864
    Abstract: A method for manufacturing a light-emitting element includes: providing a semiconductor stacked body including a first semiconductor layer, an active layer, and a second semiconductor layer, formed in this order on a substrate; exposing a surface of the first semiconductor layer by removing the substrate; and forming a protective film on the surface of the first semiconductor layer by performing steps including: forming a first layer on the surface of the first semiconductor layer by chemical vapor deposition while introducing a source gas to a film formation chamber at a first flow rate, and forming a second layer on the first layer by chemical vapor deposition while introducing a source gas to the film formation chamber at a second flow rate, the second flow rate being less than the first flow rate.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 23, 2022
    Applicant: NICHIA CORPORATION
    Inventor: Eiji MURAMOTO
  • Patent number: 11322651
    Abstract: A light-emitting element includes a first semiconductor layer, a second semiconductor layer, a light-emitting layer, a first electrode, and a second electrode. The first semiconductor layer includes gallium and nitrogen and is of an n-type. The second semiconductor layer includes gallium and nitrogen and is of a p-type. The light-emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer. The first semiconductor layer includes a first partial region and a first side surface region. The first partial region includes a first surface contacting the first electrode. The first side surface region includes a first side surface crossing a plane perpendicular to a first direction. The first direction is from the second semiconductor layer toward the first semiconductor layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 3, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Eiji Muramoto, Akinori Kishi
  • Publication number: 20210408322
    Abstract: A method of manufacturing a light-emitting element includes: providing a semiconductor structure including: a first layer containing gallium and nitrogen, a second layer of a first conductive type, the second layer containing gallium, aluminum, and nitrogen and being located on or above the first layer, an active layer located on or above the second layer, and a third layer of a second conductive type, the third layer located on or above the active layer, wherein a thickness of the first layer is larger than a thickness of the second layer; performing chemical-mechanical polishing from a first layer side to reduce the thickness of the first layer; and performing dry etching from the first layer side to remove the first layer and reduce the thickness of the second layer.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 30, 2021
    Applicant: NICHIA CORPORATION
    Inventors: Eiji MURAMOTO, Maki FUJIMOTO
  • Patent number: 11152531
    Abstract: A method of manufacturing a semiconductor device includes: providing a first member comprising: a first substrate, a semiconductor layer disposed on the first substrate and defining a first recess, and a first metal layer disposed above at least a portion other than the first recess, the first member defining a second recess in a region of a surface of the first member including a region directly above the first recess; providing a second member comprising: a second substrate, a second metal layer on or above the second substrate, a third metal layer on the second metal layer, and a fourth metal layer on the third metal layer; and bonding the first member and the second member together by heating the first metal layer and the fourth metal layer while facing each other. The third metal layer impedes interdiffusion between the second metal layer and the fourth metal layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 19, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Eiji Muramoto
  • Patent number: 10886428
    Abstract: A method of manufacturing a semiconductor element includes: a first providing step comprising providing a structure body comprising a semiconductor stacked body, the structure body including first surfaces that include surfaces defining at least one first recess; a first forming step comprising forming a first rough-surface portion at or inward of at least a portion of the surfaces defining the first recess of the structure body; a second forming step comprising forming a first metal layer at a first surface side of the structure body; a second providing step comprising providing a substrate on which a second metal layer is disposed; and a bonding step comprising heating the first metal layer and the second metal layer in a state in which the first metal layer and the second metal layer face each other.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: January 5, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Hashizume, Eiji Muramoto, Nobuyoshi Niki
  • Publication number: 20200381583
    Abstract: A method of manufacturing a semiconductor device includes: providing a first member comprising: a first substrate, a semiconductor layer disposed on the first substrate and defining a first recess, and a first metal layer disposed above at least a portion other than the first recess, the first member defining a second recess in a region of a surface of the first member including a region directly above the first recess; providing a second member comprising: a second substrate, a second metal layer on or above the second substrate, a third metal layer on the second metal layer, and a fourth metal layer on the third metal layer; and bonding the first member and the second member together by heating the first metal layer and the fourth metal layer while facing each other. The third metal layer impedes interdiffusion between the second metal layer and the fourth metal layer.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 3, 2020
    Applicant: NICHIA CORPORATION
    Inventor: Eiji MURAMOTO
  • Patent number: 10804424
    Abstract: A method for manufacturing a light emitting element includes: forming a semiconductor structure on a first substrate; providing a second substrate configured to be bonded above a side of the semiconductor structure opposite the first substrate; forming a metal layer above at least one of (i) a side of the semiconductor structure opposite the first substrate, and/or (ii) a side of the second substrate that is to be located closer to the semiconductor structure; bonding the second substrate above the semiconductor structure via a bonding member; removing the first substrate from the semiconductor structure to obtain a bonded body in which the second substrate is bonded above the semiconductor structure; and singulating the bonded body.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 13, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Eiji Muramoto
  • Patent number: 10749313
    Abstract: A method for manufacturing a semiconductor element includes: providing a nitride semiconductor layer; performing plasma treatment to at least part of a surface of the nitride semiconductor layer in an oxygen-containing atmosphere while applying bias power; after the performing of the plasma treatment, heat treating the nitride semiconductor layer in an oxygen-containing atmosphere; forming a protective film on a region of the surface of the nitride semiconductor layer where the plasma treatment was performed; and forming an electrode in a region of the surface of the nitride semiconductor layer where the protective film was not formed.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 18, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Eiji Muramoto, Akinori Kishi
  • Publication number: 20200105971
    Abstract: A light-emitting element includes a first semiconductor layer, a second semiconductor layer, a light-emitting layer, a first electrode, and a second electrode. The first semiconductor layer includes gallium and nitrogen and is of an n-type. The second semiconductor layer includes gallium and nitrogen and is of a p-type. The light-emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer. The first semiconductor layer includes a first partial region and a first side surface region. The first partial region includes a first surface contacting the first electrode. The first side surface region includes a first side surface crossing a plane perpendicular to a first direction. The first direction is from the second semiconductor layer toward the first semiconductor layer.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 2, 2020
    Applicant: NICHIA CORPORATION
    Inventors: Eiji MURAMOTO, Akinori KISHI
  • Publication number: 20200098946
    Abstract: A method of manufacturing a semiconductor element includes: a first providing step comprising providing a structure body comprising a semiconductor stacked body, the structure body including first surfaces that include surfaces defining at least one first recess; a first forming step comprising forming a first rough-surface portion at or inward of at least a portion of the surfaces defining the first recess of the structure body; a second forming step comprising forming a first metal layer at a first surface side of the structure body; a second providing step comprising providing a substrate on which a second metal layer is disposed; and a bonding step comprising heating the first metal layer and the second metal layer in a state in which the first metal layer and the second metal layer face each other.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 26, 2020
    Applicant: NICHIA CORPORATION
    Inventors: Kenji HASHIZUME, Eiji MURAMOTO, Nobuyoshi NIKI
  • Publication number: 20200006914
    Abstract: A method for manufacturing a semiconductor element includes: providing a nitride semiconductor layer; performing plasma treatment to at least part of a surface of the nitride semiconductor layer in an oxygen-containing atmosphere while applying bias power; after the performing of the plasma treatment, heat treating the nitride semiconductor layer in an oxygen-containing atmosphere; forming a protective film on a region of the surface of the nitride semiconductor layer where the plasma treatment was performed; and forming an electrode in a region of the surface of the nitride semiconductor layer where the protective film was not formed.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Inventors: Eiji MURAMOTO, Akinori KISHI
  • Publication number: 20180062025
    Abstract: A method for manufacturing a light emitting element includes: forming a semiconductor structure on a first substrate; providing a second substrate configured to be bonded above a side of the semiconductor structure opposite the first substrate; forming a metal layer above at least one of (i) a side of the semiconductor structure opposite the first substrate, and/or (ii) a side of the second substrate that is to be located closer to the semiconductor structure; bonding the second substrate above the semiconductor structure via a bonding member; removing the first substrate from the semiconductor structure to obtain a bonded body in which the second substrate is bonded above the semiconductor structure; and singulating the bonded body.
    Type: Application
    Filed: August 30, 2017
    Publication date: March 1, 2018
    Applicant: NICHIA CORPORATION
    Inventor: Eiji MURAMOTO
  • Publication number: 20160133793
    Abstract: According to one embodiment, a semiconductor light emitting element includes a conductive substrate, a bonding portion, an intermediate metal film, a first electrode, a semiconductor stacked body and a second electrode. The bonding portion is provided on the support substrate and including a first metal film. The intermediate metal film is provided on the bonding portion and having a larger linear expansion coefficient than the first metal film. The first electrode is provided on the intermediate metal film and includes a second metal film having a larger linear expansion coefficient than the intermediate metal film. The semiconductor stacked body is provided on the first electrode and including a light emitting portion. The second electrode is provided on the semiconductor stacked body.
    Type: Application
    Filed: December 28, 2015
    Publication date: May 12, 2016
    Inventors: Yasuharu SUGAWARA, Yuko KATO, Eiji MURAMOTO
  • Patent number: 9252335
    Abstract: According to one embodiment, a semiconductor light emitting element includes a conductive substrate, a bonding portion, an intermediate metal film, a first electrode, a semiconductor stacked body and a second electrode. The bonding portion is provided on the support substrate and including a first metal film. The intermediate metal film is provided on the bonding portion and having a larger linear expansion coefficient than the first metal film. The first electrode is provided on the intermediate metal film and includes a second metal film having a larger linear expansion coefficient than the intermediate metal film. The semiconductor stacked body is provided on the first electrode and including a light emitting portion. The second electrode is provided on the semiconductor stacked body.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: February 2, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuharu Sugawara, Yuko Kato, Eiji Muramoto
  • Patent number: 9147801
    Abstract: A semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer formed between the n-type semiconductor layer and the p-type semiconductor layer, and emitting light. The device further includes a p-electrode contacting to the p-type semiconductor layer, and including a first conductive oxide layer having an oxygen content lower than 40 atomic % and a second conductive oxide layer contacting to the first conductive oxide layer and having a higher oxygen content than the oxygen content of the first conductive oxide layer. The device also includes an n-electrode connecting electrically to the n-type semiconductor layer.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: September 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Eiji Muramoto, Shinya Nunoue
  • Patent number: 8994054
    Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first electrode, a second electrode, a third electrode, and a fourth electrode. The stacked structural body includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode forms an ohmic contact with the second semiconductor layer. The second electrode is translucent to light emitted from the light emitting layer. The third electrode penetrates through the second electrode and is electrically connected to the second electrode to form Shottky contact with the second semiconductor layer. The third electrode is disposed between the fourth electrode and the second semiconductor layer.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Muramoto, Shinya Nunoue, Toshiyuki Oka
  • Patent number: D722578
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiji Muramoto