Patents by Inventor Eiji Nagata
Eiji Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9949371Abstract: The problem of the invention is to provide a resin composite electrolytic copper foil having further improved heat resistance and improved plate adhesion strength when plated after desmear treatment in the work process of an additive method. The solution is to form a roughened surface having a plurality of minute projections, a surface roughness (Rz) within a range of 1.0 pm to 3.0 pm and a lightness value of not more than 30 on one surface of an electrolytic copper foil (A), and form a layer of a resin composition (B) containing a block copolymerized polyimide resin (a) having a structure that imide oligomers of a first structural unit and a second structural unit are bonded alternately and repeatedly on the roughened surface.Type: GrantFiled: August 19, 2016Date of Patent: April 17, 2018Assignees: MITSUBISHI GAS CHEMICAL COMPANY, INC., PI R&D CO., LTD.Inventors: Mitsuru Nozaki, Akihiro Nomoto, Norikatsu Akiyama, Eiji Nagata, Masashi Yano
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Publication number: 20160360615Abstract: The problem of the invention is to provide a resin composite electrolytic copper foil having further improved heat resistance and improved plate adhesion strength when plated after desmear treatment in the work process of an additive method. The solution is to form a roughened surface having a plurality of minute projections, a surface roughness (Rz) within a range of 1.0 ?m to 3.0 ?m and a lightness value of not more than 30 on one surface of an electrolytic copper foil (A), and form a layer of a resin composition (B) containing a block copolymerized polyimide resin (a) having a structure that imide oligomers of a first structural unit and a second structural unit are bonded alternately and repeatedly on the roughened surface.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Applicants: MITSUBISHI GAS CHEMICAL COMPANY, INC., PI R&D CO., LTD.Inventors: Mitsuru NOZAKI, Akihiro NOMOTO, Norikatsu AKIYAMA, Eiji NAGATA, Masashi YANO
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Patent number: 8771496Abstract: A metal composite film having an excellent heat resistance and adhesion, suited for flexible printed circuit boards capable of forming fine wirings, as well as a production process thereof, is disclosed. The metal composite film comprises an insulating film; a thermoplastic polyimide layer(s) formed on at least one surface of the insulating film; and metal layers formed on the surface of each of the thermoplastic polyimide layer(s), which metal layers are formed by electroless plating and then by electrolytic plating, respectively. Since this metal composite film has an excellent heat resistance and adhesion, and maintains the excellent adhesion after forming fine wirings, it is suitably used as a high density flexible printed circuit board having fine circuits.Type: GrantFiled: May 17, 2006Date of Patent: July 8, 2014Assignee: PI R&D Co., Ltd.Inventors: Eiji Nagata, Hiroyuki Ishii
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Publication number: 20120189859Abstract: The problem of the invention is to provide a resin composite electrolytic copper foil having further improved heat resistance and improved plate adhesion strength when plated after desmear treatment in the work process of an additive method. The solution is to form a roughened surface having a plurality of minute projections, a surface roughness (Rz) within a range of 1.0 ?m to 3.0 ?m and a lightness value of not more than 30 on one surface of an electrolytic copper foil, and form a layer of a resin composition containing a block copolymerized polyimide resin having a structure that imide oligomers of a first structural unit and a second structural unit are bonded alternately and repeatedly on the roughened surface.Type: ApplicationFiled: June 25, 2010Publication date: July 26, 2012Applicants: PI R&D CO., LTD., MITSUBISHI GAS CHEMICAL COMPANY, INC.Inventors: Mitsuru Nozaki, Akihiro Nomoto, Norikatsu Akiyama, Eiji Nagata, Masashi Yano
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Publication number: 20110281126Abstract: This invention relates to a resin composite copper foil capable of applying a copper foil with very small unevenness on a copper foil (matte) surface without deteriorating adhesion force to a resin composition of a copper-clad laminate, and more particularly to a resin composite copper foil comprising a copper foil and a polyimide resin layer wherein the polyimide resin layer contains a specific block copolymerized polyimide resin and an inorganic filler.Type: ApplicationFiled: December 10, 2009Publication date: November 17, 2011Inventors: Mitsuru Nozaki, Takabumi Oomori, Akihiro Nomoto, Norikatsu Akiyama, Eiji Nagata, Masashi Yano
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Publication number: 20110219219Abstract: This invention provides with a semiconductor integrated circuit, comprising a register map that makes correspondence between a register to which a CPU accesses and an address which specifies the register, wherein the register map includes a plurality of register maps in which assignments of address bits are rearranged in correspondence with each of a plurality of modes, and wherein any of the register maps is selected from the plurality of register maps according to the respective modes.Type: ApplicationFiled: May 18, 2011Publication date: September 8, 2011Applicant: PANASONIC CORPORATIONInventors: Yuusuke ADACHI, Eiji Nagata
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Patent number: 7989081Abstract: A resin composite copper foil comprising a copper foil and a resin layer containing a block copolymer polyimide and a maleimide compound, the resin layer being formed on one surface of the copper foil, a production process thereof, a copper-clad laminate using the resin composite copper foil, a production process of a printed wiring board using the copper-clad laminate, and a printed wiring board obtained by the above process.Type: GrantFiled: January 25, 2007Date of Patent: August 2, 2011Assignees: Mitsubishi Gas Chemical Company, Inc., PI R&D Co., Ltd.Inventors: Mitsuru Nozaki, Morio Gaku, Yasuo Tanaka, Eiji Nagata, Yasuo Kikuchi, Masashi Yano
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Patent number: 7892651Abstract: A resin composite metal foil comprising a metal foil and a layer of a block copolymer polyimide resin formed on one surface of the metal foil, a metal-foil-clad laminate using the above resin composite metal foil, a printed wiring board using the above metal-foil-clad laminate, and a process for the production of a printed wiring board comprising removing an external layer metal foil of a metal-foil-clad laminate and forming a conductor layer on an external layer insulating layer by plating, wherein the metal-foil-clad laminate comprises a layer of a block copolymer polyimide resin which layer is in contact with the external layer metal foil.Type: GrantFiled: September 13, 2005Date of Patent: February 22, 2011Assignees: Mitsubishi Gas Chemical Company, Inc., PI R&D Co., Ltd.Inventors: Takabumi Omori, Mitsuru Nozaki, Eiji Nagata, Masashi Yano
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Publication number: 20090311519Abstract: A metal composite film having an excellent heat resistance and adhesion, suited for flexible printed circuit boards capable of forming fine wirings, as well as a production process thereof, is disclosed. The metal composite film comprises an insulating film; a thermoplastic polyimide layer(s) formed on at least one surface of the insulating film; and metal layers formed on the surface of each of the thermoplastic polyimide layer(s), which metal layers are formed by electroless plating and then by electrolytic plating, respectively. Since this metal composite film has an excellent heat resistance and adhesion, and maintains the excellent adhesion after forming fine wirings, it is suitably used as a high density flexible printed circuit board having fine circuits.Type: ApplicationFiled: May 17, 2006Publication date: December 17, 2009Inventors: Eiji Nagata, Hiroyuki Ishii
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Publication number: 20090198878Abstract: The information processing system is comprised of: a first nonvolatile storage device in which a plurality of first programs for initiating the information processing system, and duplications of the plural first programs have been stored in blocks different from each other; a second volatile storage device to which the plurality of first programs are transferred; a third nonvolatile storage device into which a second program for executing the plural first programs is stored; and a CPU (Central Processing Unit) for executing the plural first programs.Type: ApplicationFiled: February 2, 2009Publication date: August 6, 2009Inventors: Shinji NISHIHARA, Eiji NAGATA
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Patent number: 7346871Abstract: A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.Type: GrantFiled: December 13, 2005Date of Patent: March 18, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Fumihito Watanuki, Eiji Nagata
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Publication number: 20070217096Abstract: In an integrated circuit apparatus made up of three or more integrated circuits which are supplied with power from three or more power supply sources that can be subjected to individually-controllable shutoff and which are sequentially subjected to interruption of power supply, control of a power shutoff circuit inserted into a signal line between integrated circuits is facilitated without regard to the physical layout of integrated circuits. A power shutoff control signal is imparted to a power shutoff circuit which is inserted into a signal line for interconnecting integrated circuits and which controls an output from a power shutoff circuit to a fixed state during shutoff of power to a connection-target integrated circuit. Accordingly, the integrated circuits are selected in sequence of interruption of power supply.Type: ApplicationFiled: March 6, 2007Publication date: September 20, 2007Inventors: Kenichi Ishida, Yosikazu Nishikawa, Eiji Nagata
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Publication number: 20070172674Abstract: A resin composite copper foil comprising a copper foil and a resin layer containing a block copolymer polyimide and a maleimide compound, the resin layer being formed on one surface of the copper foil, a production process thereof, a copper-clad laminate using the resin composite copper foil, a production process of a printed wiring board using the copper-clad laminate, and a printed wiring board obtained by the above process.Type: ApplicationFiled: January 25, 2007Publication date: July 26, 2007Inventors: Mitsuru Nozaki, Morio Gaku, Yasuo Tanaka, Eiji Nagata, Yasuo Kikuchi, Masashi Yano
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Patent number: 7146550Abstract: In order to avoid generation of a routing complexity of LSI and a signal rounding due to insertion of the isolation testing circuit, if a plurality of IPs are incorporated into LSI, the present invention provides an isolation testing circuits having test switching selectors 731 to 736 for selecting any one of a test input signal (or a test input transit signal) and a normal input signal, and test signal transit buffers 721 to 726 for relaying the test input signal (or the test input transit signal) are formed in respective IP blocks 701 to 706 incorporated into an LSI. Adjacent isolation testing circuits are connected mutually based on a floor plan or layout placement information such that a wiring length of a test input signal 709 and test input transit signals 710 to 714, which are connected in a single stroke of a pen, can be reduced shortest.Type: GrantFiled: March 5, 2004Date of Patent: December 5, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Eiji Nagata
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Publication number: 20060124968Abstract: A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.Type: ApplicationFiled: December 13, 2005Publication date: June 15, 2006Inventors: Fumihito Watanuki, Eiji Nagata
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Publication number: 20060054589Abstract: A resin composite metal foil comprising a metal foil and a layer of a block copolymer polyimide resin formed on one surface of the metal foil, a metal-foil-clad laminate using the above resin composite metal foil, a printed wiring board using the above metal-foil-clad laminate, and a process for the production of a printed wiring board comprising removing an external layer metal foil of a metal-foil-clad laminate and forming a conductor layer on an external layer insulating layer by plating, wherein the metal-foil-clad laminate comprises a layer of a block copolymer polyimide resin which layer is in contact with the external layer metal foil.Type: ApplicationFiled: September 13, 2005Publication date: March 16, 2006Inventors: Takabumi Omori, Mitsuru Nozaki, Eiji Nagata, Masashi Yano
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Patent number: 6882175Abstract: An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuits 112 and 114 are respectively provided in blocks 102 and 104 that communicate signals with one another, and interface control circuit 202 dynamically controls respective input levels of gate circuits 112 and 114. In other words, the circuit 202 fixes an input level of gate circuit 112 or 114 in a block whose power supply is ON to āLā, and thereby compulsively fixes an output level of the gate circuit to āLā.Type: GrantFiled: June 13, 2003Date of Patent: April 19, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Isao Motegi, Eiji Nagata
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Publication number: 20040181720Abstract: In order to avoid generation of a routing complexity of LSI and a signal rounding due to insertion of the isolation testing circuit, if a plurality of IPs are incorporated into LSI, the present invention provides an isolation testing circuits having test switching selectors 731 to 736 for selecting any one of a test input signal (or a test input transit signal) and a normal input signal, and test signal transit buffers 721 to 726 for relaying the test input signal (or the test input transit signal) are formed in respective IP blocks 701 to 706 incorporated into an LSI. Adjacent isolation testing circuits are connected mutually based on a floor plan or layout placement information such that a wiring length of a test input signal 709 and test input transit signals 710 to 714, which are connected in a single stroke of a pen, can be reduced shortest.Type: ApplicationFiled: March 5, 2004Publication date: September 16, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Eiji Nagata
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Publication number: 20040010726Abstract: An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuits 112 and 114 are respectively provided in blocks 102 and 104 that communicate signals with one another, and interface control circuit 202 dynamically controls respective input levels of gate circuits 112 and 114. In other words, the circuit 202 fixes an input level of gate circuit 112 or 114 in a block whose power supply is ON to “L”, and thereby compulsively fixes an output level of the gate circuit to “L”.Type: ApplicationFiled: June 13, 2003Publication date: January 15, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Isao Motegi, Eiji Nagata
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Patent number: 4841353Abstract: A transistor device for a microwave oscillating element having an FET transistor chip and a package encapsulating the chip therein. In order to avoid any affection of the external circuit to the input impedance of the transistor device and to make the phase rotation low at a frequency band higher than the X band, a conductor element is provided within the package to connect the drain electrode of the chip and a corresponding terminal of the package. The conductor element has an inductance to provide a sufficient high impedance at the intended frequency band. The conductor element is supported on an insulator plate fixedly mounted within the package.Type: GrantFiled: November 24, 1987Date of Patent: June 20, 1989Assignee: NEC CorporationInventors: Kenzo Wada, Eiji Nagata