Patents by Inventor Eiji Nagata

Eiji Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9949371
    Abstract: The problem of the invention is to provide a resin composite electrolytic copper foil having further improved heat resistance and improved plate adhesion strength when plated after desmear treatment in the work process of an additive method. The solution is to form a roughened surface having a plurality of minute projections, a surface roughness (Rz) within a range of 1.0 pm to 3.0 pm and a lightness value of not more than 30 on one surface of an electrolytic copper foil (A), and form a layer of a resin composition (B) containing a block copolymerized polyimide resin (a) having a structure that imide oligomers of a first structural unit and a second structural unit are bonded alternately and repeatedly on the roughened surface.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: April 17, 2018
    Assignees: MITSUBISHI GAS CHEMICAL COMPANY, INC., PI R&D CO., LTD.
    Inventors: Mitsuru Nozaki, Akihiro Nomoto, Norikatsu Akiyama, Eiji Nagata, Masashi Yano
  • Publication number: 20160360615
    Abstract: The problem of the invention is to provide a resin composite electrolytic copper foil having further improved heat resistance and improved plate adhesion strength when plated after desmear treatment in the work process of an additive method. The solution is to form a roughened surface having a plurality of minute projections, a surface roughness (Rz) within a range of 1.0 ?m to 3.0 ?m and a lightness value of not more than 30 on one surface of an electrolytic copper foil (A), and form a layer of a resin composition (B) containing a block copolymerized polyimide resin (a) having a structure that imide oligomers of a first structural unit and a second structural unit are bonded alternately and repeatedly on the roughened surface.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Applicants: MITSUBISHI GAS CHEMICAL COMPANY, INC., PI R&D CO., LTD.
    Inventors: Mitsuru NOZAKI, Akihiro NOMOTO, Norikatsu AKIYAMA, Eiji NAGATA, Masashi YANO
  • Patent number: 8771496
    Abstract: A metal composite film having an excellent heat resistance and adhesion, suited for flexible printed circuit boards capable of forming fine wirings, as well as a production process thereof, is disclosed. The metal composite film comprises an insulating film; a thermoplastic polyimide layer(s) formed on at least one surface of the insulating film; and metal layers formed on the surface of each of the thermoplastic polyimide layer(s), which metal layers are formed by electroless plating and then by electrolytic plating, respectively. Since this metal composite film has an excellent heat resistance and adhesion, and maintains the excellent adhesion after forming fine wirings, it is suitably used as a high density flexible printed circuit board having fine circuits.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: July 8, 2014
    Assignee: PI R&D Co., Ltd.
    Inventors: Eiji Nagata, Hiroyuki Ishii
  • Publication number: 20120189859
    Abstract: The problem of the invention is to provide a resin composite electrolytic copper foil having further improved heat resistance and improved plate adhesion strength when plated after desmear treatment in the work process of an additive method. The solution is to form a roughened surface having a plurality of minute projections, a surface roughness (Rz) within a range of 1.0 ?m to 3.0 ?m and a lightness value of not more than 30 on one surface of an electrolytic copper foil, and form a layer of a resin composition containing a block copolymerized polyimide resin having a structure that imide oligomers of a first structural unit and a second structural unit are bonded alternately and repeatedly on the roughened surface.
    Type: Application
    Filed: June 25, 2010
    Publication date: July 26, 2012
    Applicants: PI R&D CO., LTD., MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Mitsuru Nozaki, Akihiro Nomoto, Norikatsu Akiyama, Eiji Nagata, Masashi Yano
  • Publication number: 20110281126
    Abstract: This invention relates to a resin composite copper foil capable of applying a copper foil with very small unevenness on a copper foil (matte) surface without deteriorating adhesion force to a resin composition of a copper-clad laminate, and more particularly to a resin composite copper foil comprising a copper foil and a polyimide resin layer wherein the polyimide resin layer contains a specific block copolymerized polyimide resin and an inorganic filler.
    Type: Application
    Filed: December 10, 2009
    Publication date: November 17, 2011
    Inventors: Mitsuru Nozaki, Takabumi Oomori, Akihiro Nomoto, Norikatsu Akiyama, Eiji Nagata, Masashi Yano
  • Publication number: 20110219219
    Abstract: This invention provides with a semiconductor integrated circuit, comprising a register map that makes correspondence between a register to which a CPU accesses and an address which specifies the register, wherein the register map includes a plurality of register maps in which assignments of address bits are rearranged in correspondence with each of a plurality of modes, and wherein any of the register maps is selected from the plurality of register maps according to the respective modes.
    Type: Application
    Filed: May 18, 2011
    Publication date: September 8, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Yuusuke ADACHI, Eiji Nagata
  • Patent number: 7989081
    Abstract: A resin composite copper foil comprising a copper foil and a resin layer containing a block copolymer polyimide and a maleimide compound, the resin layer being formed on one surface of the copper foil, a production process thereof, a copper-clad laminate using the resin composite copper foil, a production process of a printed wiring board using the copper-clad laminate, and a printed wiring board obtained by the above process.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: August 2, 2011
    Assignees: Mitsubishi Gas Chemical Company, Inc., PI R&D Co., Ltd.
    Inventors: Mitsuru Nozaki, Morio Gaku, Yasuo Tanaka, Eiji Nagata, Yasuo Kikuchi, Masashi Yano
  • Patent number: 7892651
    Abstract: A resin composite metal foil comprising a metal foil and a layer of a block copolymer polyimide resin formed on one surface of the metal foil, a metal-foil-clad laminate using the above resin composite metal foil, a printed wiring board using the above metal-foil-clad laminate, and a process for the production of a printed wiring board comprising removing an external layer metal foil of a metal-foil-clad laminate and forming a conductor layer on an external layer insulating layer by plating, wherein the metal-foil-clad laminate comprises a layer of a block copolymer polyimide resin which layer is in contact with the external layer metal foil.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: February 22, 2011
    Assignees: Mitsubishi Gas Chemical Company, Inc., PI R&D Co., Ltd.
    Inventors: Takabumi Omori, Mitsuru Nozaki, Eiji Nagata, Masashi Yano
  • Publication number: 20090311519
    Abstract: A metal composite film having an excellent heat resistance and adhesion, suited for flexible printed circuit boards capable of forming fine wirings, as well as a production process thereof, is disclosed. The metal composite film comprises an insulating film; a thermoplastic polyimide layer(s) formed on at least one surface of the insulating film; and metal layers formed on the surface of each of the thermoplastic polyimide layer(s), which metal layers are formed by electroless plating and then by electrolytic plating, respectively. Since this metal composite film has an excellent heat resistance and adhesion, and maintains the excellent adhesion after forming fine wirings, it is suitably used as a high density flexible printed circuit board having fine circuits.
    Type: Application
    Filed: May 17, 2006
    Publication date: December 17, 2009
    Inventors: Eiji Nagata, Hiroyuki Ishii
  • Publication number: 20090198878
    Abstract: The information processing system is comprised of: a first nonvolatile storage device in which a plurality of first programs for initiating the information processing system, and duplications of the plural first programs have been stored in blocks different from each other; a second volatile storage device to which the plurality of first programs are transferred; a third nonvolatile storage device into which a second program for executing the plural first programs is stored; and a CPU (Central Processing Unit) for executing the plural first programs.
    Type: Application
    Filed: February 2, 2009
    Publication date: August 6, 2009
    Inventors: Shinji NISHIHARA, Eiji NAGATA
  • Patent number: 7346871
    Abstract: A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: March 18, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Fumihito Watanuki, Eiji Nagata
  • Publication number: 20070217096
    Abstract: In an integrated circuit apparatus made up of three or more integrated circuits which are supplied with power from three or more power supply sources that can be subjected to individually-controllable shutoff and which are sequentially subjected to interruption of power supply, control of a power shutoff circuit inserted into a signal line between integrated circuits is facilitated without regard to the physical layout of integrated circuits. A power shutoff control signal is imparted to a power shutoff circuit which is inserted into a signal line for interconnecting integrated circuits and which controls an output from a power shutoff circuit to a fixed state during shutoff of power to a connection-target integrated circuit. Accordingly, the integrated circuits are selected in sequence of interruption of power supply.
    Type: Application
    Filed: March 6, 2007
    Publication date: September 20, 2007
    Inventors: Kenichi Ishida, Yosikazu Nishikawa, Eiji Nagata
  • Publication number: 20070172674
    Abstract: A resin composite copper foil comprising a copper foil and a resin layer containing a block copolymer polyimide and a maleimide compound, the resin layer being formed on one surface of the copper foil, a production process thereof, a copper-clad laminate using the resin composite copper foil, a production process of a printed wiring board using the copper-clad laminate, and a printed wiring board obtained by the above process.
    Type: Application
    Filed: January 25, 2007
    Publication date: July 26, 2007
    Inventors: Mitsuru Nozaki, Morio Gaku, Yasuo Tanaka, Eiji Nagata, Yasuo Kikuchi, Masashi Yano
  • Patent number: 7146550
    Abstract: In order to avoid generation of a routing complexity of LSI and a signal rounding due to insertion of the isolation testing circuit, if a plurality of IPs are incorporated into LSI, the present invention provides an isolation testing circuits having test switching selectors 731 to 736 for selecting any one of a test input signal (or a test input transit signal) and a normal input signal, and test signal transit buffers 721 to 726 for relaying the test input signal (or the test input transit signal) are formed in respective IP blocks 701 to 706 incorporated into an LSI. Adjacent isolation testing circuits are connected mutually based on a floor plan or layout placement information such that a wiring length of a test input signal 709 and test input transit signals 710 to 714, which are connected in a single stroke of a pen, can be reduced shortest.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: December 5, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Eiji Nagata
  • Publication number: 20060124968
    Abstract: A method of estimating a wiring complexity degree in a semiconductor integrated circuit with a multi-layered wiring, which has a wiring structure including at least two layers or more, in laying signal wirings, includes a step of predicting a power-supply wiring space used in the semiconductor integrated circuit, a step of dividing the predicted power-supply wiring space onto respective wiring layers, and a step of estimating a complexity degree at a time of laying signal wirings, based on the predicted power-supply wiring space and a wiring specification in respective wiring layers every wiring layer.
    Type: Application
    Filed: December 13, 2005
    Publication date: June 15, 2006
    Inventors: Fumihito Watanuki, Eiji Nagata
  • Publication number: 20060054589
    Abstract: A resin composite metal foil comprising a metal foil and a layer of a block copolymer polyimide resin formed on one surface of the metal foil, a metal-foil-clad laminate using the above resin composite metal foil, a printed wiring board using the above metal-foil-clad laminate, and a process for the production of a printed wiring board comprising removing an external layer metal foil of a metal-foil-clad laminate and forming a conductor layer on an external layer insulating layer by plating, wherein the metal-foil-clad laminate comprises a layer of a block copolymer polyimide resin which layer is in contact with the external layer metal foil.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 16, 2006
    Inventors: Takabumi Omori, Mitsuru Nozaki, Eiji Nagata, Masashi Yano
  • Patent number: 6882175
    Abstract: An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuits 112 and 114 are respectively provided in blocks 102 and 104 that communicate signals with one another, and interface control circuit 202 dynamically controls respective input levels of gate circuits 112 and 114. In other words, the circuit 202 fixes an input level of gate circuit 112 or 114 in a block whose power supply is ON to ā€œLā€, and thereby compulsively fixes an output level of the gate circuit to ā€œLā€.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: April 19, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Motegi, Eiji Nagata
  • Publication number: 20040181720
    Abstract: In order to avoid generation of a routing complexity of LSI and a signal rounding due to insertion of the isolation testing circuit, if a plurality of IPs are incorporated into LSI, the present invention provides an isolation testing circuits having test switching selectors 731 to 736 for selecting any one of a test input signal (or a test input transit signal) and a normal input signal, and test signal transit buffers 721 to 726 for relaying the test input signal (or the test input transit signal) are formed in respective IP blocks 701 to 706 incorporated into an LSI. Adjacent isolation testing circuits are connected mutually based on a floor plan or layout placement information such that a wiring length of a test input signal 709 and test input transit signals 710 to 714, which are connected in a single stroke of a pen, can be reduced shortest.
    Type: Application
    Filed: March 5, 2004
    Publication date: September 16, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Eiji Nagata
  • Publication number: 20040010726
    Abstract: An inter-block interface circuit which effectively prevents occurrences of inconveniences (for example, such that a shoot-through current flows due to unsteady potential in wiring) caused by switching off a power supply of a block, using simple circuitry, in LSI such that signals are communicated between the blocks and the power supplies of the blocks are interrupted independently. In the circuit, gate circuits 112 and 114 are respectively provided in blocks 102 and 104 that communicate signals with one another, and interface control circuit 202 dynamically controls respective input levels of gate circuits 112 and 114. In other words, the circuit 202 fixes an input level of gate circuit 112 or 114 in a block whose power supply is ON to “L”, and thereby compulsively fixes an output level of the gate circuit to “L”.
    Type: Application
    Filed: June 13, 2003
    Publication date: January 15, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Motegi, Eiji Nagata
  • Patent number: 4841353
    Abstract: A transistor device for a microwave oscillating element having an FET transistor chip and a package encapsulating the chip therein. In order to avoid any affection of the external circuit to the input impedance of the transistor device and to make the phase rotation low at a frequency band higher than the X band, a conductor element is provided within the package to connect the drain electrode of the chip and a corresponding terminal of the package. The conductor element has an inductance to provide a sufficient high impedance at the intended frequency band. The conductor element is supported on an insulator plate fixedly mounted within the package.
    Type: Grant
    Filed: November 24, 1987
    Date of Patent: June 20, 1989
    Assignee: NEC Corporation
    Inventors: Kenzo Wada, Eiji Nagata