Patents by Inventor EINAT ZEVULUN

EINAT ZEVULUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10359955
    Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a volatile memory configured to store a first copy of a control table associated with the non-volatile memory. The controller is configured to perform a first update of a portion of the first copy of the control table in response to a first request, to initiate a second update of a second copy of the control table at the non-volatile memory based on the first update, and to execute a second request for access to the non-volatile memory concurrently with of the second update. The controller is configured to perform non-blocking control sync operations and non-blocking consolidation operations asynchronously, wherein non-blocking consolidation operations are atomic operations that include concurrent evacuation and compaction of an update layer to a cached address translation table in the volatile memory.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 23, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Karin Inbar, Michael Ionin, Einat Zevulun, Einat Lev
  • Publication number: 20180239547
    Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a volatile memory configured to store a first copy of a control table associated with the non-volatile memory. The controller is configured to perform a first update of a portion of the first copy of the control table in response to a first request, to initiate a second update of a second copy of the control table at the non-volatile memory based on the first update, and to execute a second request for access to the non-volatile memory concurrently with of the second update. The controller is configured to perform non-blocking control sync operations and non-blocking consolidation operations asynchronously, wherein non-blocking consolidation operations are atomic operations that include concurrent evacuation and compaction of an update layer to a cached address translation table in the volatile memory.
    Type: Application
    Filed: June 6, 2017
    Publication date: August 23, 2018
    Inventors: Karin Inbar, MICHAEL IONIN, EINAT ZEVULUN, EINAT LEV