Patents by Inventor Eing-Chieh Chen

Eing-Chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6716676
    Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on the substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced heat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: April 6, 2004
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Eing-Chieh Chen, Cheng-Yuan Lai, Tzu-Yi Tien
  • Patent number: 6650015
    Abstract: A cavity-down ball grid array package includes a substrate having a through cavity provided therein. A heat sink is attached to the substrate and a semiconductor chip in the cavity is attached to the heat sink and electrically connected to the substrate. A ball grid array is on the substrate and on the semiconductor chip.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: November 18, 2003
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Eing-Chieh Chen, Shiu-Tai Tzung, Ting-Ke Chai, Jeng-Yuan Lai, Candy Tien
  • Publication number: 20030146508
    Abstract: A cavity-down ball grid array package includes a substrate having a through cavity provided therein. A heat sink is attached to the substrate and a semiconductor chip in the cavity is attached to the heat sink and electrically connected to the substrate. A ball grid array is on the substrate and on the semiconductor chip.
    Type: Application
    Filed: June 14, 2002
    Publication date: August 7, 2003
    Inventors: Eing-Chieh Chen, Shiu-Tai Tzung, Ting-Ke Chai, Jeng-Yuan Lai, Candy Tien
  • Publication number: 20030020151
    Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on the substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced heat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.
    Type: Application
    Filed: September 19, 2002
    Publication date: January 30, 2003
    Applicant: Siliconware Precision Industries Co., Ltd
    Inventors: Eing-Chieh Chen, Cheng-Yuan Lai, Tzu-Yi Tien
  • Patent number: 6472741
    Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on he substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced beat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.
    Type: Grant
    Filed: July 14, 2001
    Date of Patent: October 29, 2002
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Eing-Chieh Chen, Cheng-Yuan Lai, Tzu-Yi Tien