Abstract: On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end portion on the first chip side are arranged having a steplike shift in a direction apart from the first chip side with decreasing distance from the center portion to the end portion on the first chip side.

Abstract: The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

Abstract: In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply section of a semiconductor integrated circuit chip with power from an external power supply are connected with bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. Furthermore, the conductive leads connected to a GND for supplying the power supply section of the semiconductor integrated circuit chip with a grounding potential are connected with the bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires.

Abstract: A testing method of semiconductor integrated circuit wherein the quality of diffusion for semiconductor chips can be tested before the semiconductor chips become packaged semiconductor integrated circuits is provided. Input data is set, and circuit current values I(L) and I(H) obtained for each of a plurality of circuit areas are compared with first test pass ranges I1(L) and I1(H) to extract articles within the first test pass (S2), and the current values of the circuit areas determined to be articles within the first test pass and second test pass ranges I2(L), and I2(H) determined based on these current values are compared, thereby conducting a retest to extract circuit areas within the second test pass. The current values may be replaced by the voltage values.

Abstract: On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end portion on the first chip side are arranged having a steplike shift in a direction apart from the first chip side with decreasing distance from the center portion to the end portion on the first chip side.

Abstract: A testing method of semiconductor integrated circuit wherein the quality of diffusion for semiconductor chips can be tested before the semiconductor chips become packaged semiconductor integrated circuits is provided. Input data is set, and circuit current values I(L) and I(H) obtained for each of a plurality of circuit areas are compared with first test pass ranges I1(L) and I1(H) to extract articles within the first test pass (S2), and the current values of the circuit areas determined to be articles within the first test pass and second test pass ranges I2(L), and I2(H) determined based on these current values are compared, thereby conducting a retest to extract circuit areas within the second test pass. The current values may be replaced by the voltage values.

Abstract: A PDP-driving semiconductor integrated circuit includes a plurality of PDP drivers each for converting an input signal into a high-voltage pulse having an amplitude greater than that of the input signal and outputting the high-voltage pulse. The PDP-driving semiconductor integrated circuit has a function of performing sequential operation in which the PDP drivers operate at different timings and sequentially output the high-voltage pulses and a function of performing simultaneous operation in which the PDP drivers operate at the same timing and output the high-voltage pulses at a time. In each of the sequential operation and the simultaneous operation, at least one of the speed of change in voltage level of the high-voltage pulse from a low level to a high level and the speed of change in voltage level of the high-voltage pulse from the high level to the low level is controlled.

Abstract: It is aimed to reduce the area of an output circuit in a capacitive load driving circuit capable of high voltage output, such as a PDP scan driver for driving a plasma display panel. To achieve this, there are provided an arbitrary number of N-type MOS transistors 001, 002, . . . , and 003 including grounded sources and gates receiving a control signal, diodes 004, 005, . . . , and 006 paired with the N-type MOS transistors 001, 002, . . . , and 003, respectively, and including cathodes connected to drains of the N-type MOS transistors 001, 002, . . . , and 003 and anode, all connected to a first node 044, the number of diodes being the same as the number of N-type MOS transistors, and a first P-type MOS transistor 015 having a drain connected to the first node 044, a gate receiving a control signal and a source connected to a high voltage source.

Abstract: In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply section of a semiconductor integrated circuit chip with power from an external power supply are connected with bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. Furthermore, the conductive leads connected to a GND for supplying the power supply section of the semiconductor integrated circuit chip with a grounding potential are connected with the bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires.

Abstract: The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, wherein a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.

Abstract: A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each source terminal thereof is respectively connected to the three power supplies, and a sequential circuit that outputs control signals controlling the transistors. The sequential circuit outputs control signals that make the first and the third transistors be switched in a complementary manner in an initial state, and make the second and the third transistors be switched in a state that it is released from the initial state.

Abstract: The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

Abstract: The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

Abstract: A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a level shift unit having PMOS transistors and NMOS transistors, and a CMOS output unit having a PMOS transistor and an NMOS transistor. The source, drain and gate of one PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact. The source, drain and gate of a second PMOS transistor are respectively connected to a high voltage power supply, the second contact and the first contact. The source of one NMOS transistor is grounded, the drain thereof is connected to the first contact, and the gate thereof receives a low voltage signal. The source of a second NMOS transistor is grounded, the drain thereof is connected to the second contact, and the gate thereof receives a low voltage signal.

Abstract: A semiconductor integrated circuit device capable of securely preventing the output from becoming indefinite even when power is turned ON or OFF or even in a transient state in which the power voltage varies abruptly. In the semiconductor integrated circuit device, a protection circuit compares the power voltage from a first power supply terminal with a reference voltage, detects power ON, power OFF and abrupt power voltage variation, and outputs a reset command signal so that the output at the output terminal has a high impedance at the time of power ON, power OFF and abrupt power voltage variation.

Abstract: A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each source terminal thereof is respectively connected to the three power supplies, and a sequential circuit that outputs control signals controlling the transistors. The sequential circuit outputs control signals that make the first and the third transistors be switched in a complementary manner in an initial state, and make the second and the third transistors be switched in a state that it is released from the initial state.

Abstract: A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a level shift unit having PMOS transistors and NMOS transistors, and a CMOS output unit having a PMOS transistor and an NMOS transistor. The source, drain and gate of one PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact. The source, drain and gate of a second PMOS transistor are respectively connected to a high voltage power supply, the second contact and the first contact. The source of one NMOS transistor is grounded, the drain thereof is connected to the first contact, and the gate thereof receives a low voltage signal. The source of a second NMOS transistor is grounded, the drain thereof is connected to the second contact, and the gate thereof receives a low voltage signal.

Abstract: The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize the output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of the cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, where a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.

Abstract: The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

Abstract: An image reading system prescans and/or scans a film with magnetic recording and image data to be stored in a film cartridge after the film is developed. The image reading system employs a one-dimensional CCD and is capable of recording/reading retrievable ID numbers on a magnetic recording part. A thumbnail display simultaneously displays all image and magnetic information of all frames of a film, and selected frames to be scanned can be easily identified and compared after obtaining the image data of such film through prescanning. Magnetic recording information and image information are rapidly read during prescanning and selected frames are then scanned with more refinement as compared to the coarse scanning of the film during prescanning.