Abstract: A network device receives data packets from a network adaptor. A low latency memory has a first read/write performance. A high latency memory has a second read/write performance that is slower than the first read/write performance of the low latency memory. An interface controller uses an address check circuit and values stored in registers to determine whether a read or write operation relates to header portions of the data packets. The interface controller stores header portions of the data packets in the low latency memory and data portions of the data packets in the high latency memory. The registers include base address, buffer pool size, maximum individual buffer size, and header size registers. Alternately the registers include base address, mask, maximum individual buffer size, and header size registers.

Abstract: A method of broadcasting a packet to the ports belonging to one VLAN of a network, whereas the network has multiple network switches. Each network switch has its own local ports and a local VLAN table. Each local VLAN table stores local port membership of its network switch, and switch membership per VLAN identifier. The local VLAN table is accessed by a VLAN identifier which is stored in the packet, and retrieves the local port membership and switch membership associated with the VLAN identifier. A copy of the packet is provided to each local port and to each switch retrieved from said local VLAN table.

Abstract: A data network including at least one crossbar, wherein each crossbar comprises N ports and a plurality N of devices each associated with and connected to one port of one of the crossbars. Each one port of one crossbar includes an input buffer, a plurality N?1 of port output buffers, a plurality N?1 of fullness sensors, shutoff devices. The input buffer receives messages from the device connected to its port and sends the messages to the other ports of the one crossbar. Each port output buffers corresponds to one of the other ports, wherein each port output buffer receives the messages only from the input buffer of its associated other port. Each fullness sensor is associated with one port output buffer and measures the fullness state of its associated port output buffer.

Abstract: A crossbar for communicating with at least one device, the crossbar comprises N ports. Each one of the N ports comprises a link logic unit to receive messages and data from a respective device, N?1 output buffers each corresponding to another one of the N?1 ports and a port arbiter to select one of the N?1 output buffers to output data to the respective device. The stored data is transferred to the corresponding output buffer of a selected one of the other one of the N ports.

Abstract: A network switch which includes a plurality of output ports, at least one input port and a queuing manager. Each output port has a control unit associated therewith. The input port receives incoming data destined for various ones of the output ports. The queuing manager directs the incoming data to their destination output ports. Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask. The output queue stores the incoming data destined for its associated output port. The sensor senses when the output queue reaches a fullness or an emptiness state. The HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.

Abstract: A network switch which includes a plurality of output ports, at least one input port and a queuing manager. Each output port has a control unit associated therewith. The input port receives incoming data destined for various ones of the output ports. The queuing manager directs the incoming data to their destination output ports. Each control unit includes an output queue, a fullness/emptiness sensor and a head of line (HOL) mask. The output queue stores the incoming data destined for its associated output port. The sensor senses when the output queue reaches a fullness or an emptiness state. The HOL mask is connected to the output of the sensor and blocks inflow of the incoming data to the output queue when the sensor senses the fullness state and for enabling inflow when the sensor senses the emptiness state.

Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein a each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: A method providing automating detection of configuration between an adapter device and a DRAM device. Such a method a determines, in the adapter memory, the DRAM configuration, making it easier to change DRAM configuration in an existing board without the need to modify configuration pins in the existing board. A method for determining a configuration type in an Asynchronous Transfer Mode (ATM) communications network comprising the steps of providing an ATM adapter, the ATM adapter having an ATM adapter memory, providing a DRAM device, the DRAM device having a DRAM configuration, providing a link to connect the ATM adapter and the DRAM device, assuming, in the ATM adapter memory, a first DRAM configuration, verifying the step of assuming, and repeating the steps of assuming and verifying until the first DRAM configuration is determined.