Abstract: A radio receiver device determines whether a digital radio signal includes a predetermined cyclic preamble. An input portion samples the digital radio signal and generates a plurality of samples for storage in a buffer. A first autocorrelator correlates first and second subsets of the samples to generate a first correlation metric, the second subset having been stored in the buffer earlier than said first subset by an even integer multiple of half of the preamble period. A second autocorrelator correlates first and third subsets of the plurality of samples to generate a second correlation metric, the third subset having been stored in the buffer earlier than said first subset by an odd integer multiple of half of the preamble period. A processing portion calculates a difference between the correlation metrics and determines that the radio signal includes the predetermined cyclic preamble when the difference is greater than a threshold value.

Abstract: A demodulator for a digital radio receiver comprises a frequency discriminator and a Viterbi decoder. The frequency discriminator receives a series digital signal samples representative of an FSK-modulated signal and performs frequency discrimination on the digital signal samples to generate a series of frequency samples. Each frequency sample represents an instantaneous frequency of the signal in a respective frequency-sample period. There are an integer oversampling factor, N>1, of frequency-sample periods in each symbol period. The Viterbi decoder receives the series of frequency samples, determines branch metrics for each symbol period by determining distances between a vector of N successive frequency samples and each of a plurality of reference waveform vectors, each comprising N elements. It use the branch metrics in a Viterbi process to output demodulated symbol values corresponding to a maximum-likelihood decoding of the FSK-modulated signal.

Abstract: A radio receiver device is arranged to receive a radio signal including a data packet having an address portion and a payload portion, said radio receiver comprising: a first demodulation circuit portion arranged to demodulate the data packet and produce a first estimate of the address portion and a first estimate of the payload portion; a second demodulation circuit portion arranged to demodulate the data packet and produce a second estimate of the payload portion; a first comparison circuit portion arranged to compare said first and second estimates of the payload portion and produce a flag only if they are identical; and a second comparison circuit portion arranged, upon receipt of said flag, to compare said first estimate of the address portion to an expected address portion and to discard the data packet if they are not identical.

Abstract: A radio communication apparatus receives or generates a base address seed, and generates data-channel access addresses from the seed. Each access address corresponds to a respective data-channel identifier, and is generated by setting a bit at a common first bit position to the value of a bit at a first common predetermined bit position in the base address seed or in the respective data-channel identifier; by setting a bit at a common second bit position to the bitwise complement of this value; and by setting one or more remaining bit positions in dependence on values at one or more bit positions in the base address seed and one or more bit positions in the respective data-channel identifier that are not the first common predetermined bit position. The apparatus can send or receive a radio data packet comprising an access address from the generated set.

Abstract: A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet; a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information; an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern.

Abstract: A radio communication apparatus receives or generates a base address seed, and generates data-channel access addresses from the seed. Each access address corresponds to a respective data-channel identifier, and is generated by setting a bit at a common first bit position to the value of a bit at a first common predetermined bit position in the base address seed or in the respective data-channel identifier; by setting a bit at a common second bit position to the bitwise complement of this value; and by setting one or more remaining bit positions in dependence on values at one or more bit positions in the base address seed and one or more bit positions in the respective data-channel identifier that are not the first common predetermined bit position. The apparatus can send or receive a radio data packet comprising an access address from the generated set.

Abstract: A radio receiver device is arranged to receive a radio signal including a data packet having an address portion and a payload portion, said radio receiver comprising: a first demodulation circuit portion arranged to demodulate the data packet and produce a first estimate of the address portion and a first estimate of the payload portion; a second demodulation circuit portion arranged to demodulate the data packet and produce a second estimate of the payload portion; a first comparison circuit portion arranged to compare said first and second estimates of the payload portion and produce a flag only if they are identical; and a second comparison circuit portion arranged, upon receipt of said flag, to compare said first estimate of the address portion to an expected address portion and to discard the data packet if they are not identical.

Abstract: A radio receiver device is arranged to receive a radio signal modulated with a data packet including an address portion. The radio receiver comprises: a synchronisation circuit portion arranged to produce synchronization information corresponding to the data packet; a demodulation circuit portion comprising a correlator, wherein said demodulation circuit portion is arranged to receive the radio signal and to produce an estimate of the address portion comprising a plurality of demodulated bits using said correlator and the synchronisation information; an address checking circuit portion arranged to receive the plurality of demodulated bits, to check said plurality of demodulated bits for a predetermined bit pattern, and to produce a match flag if it determines that the plurality of demodulated bits corresponds to the predetermined bit pattern.

Abstract: A method of processing a digitally encoded radio signal (102) comprising a bit to be determined is disclosed. The method comprises correlating a first bit sequence (103) comprising the bit with a plurality of predetermined filters (104a-h) to create a first set of filter coefficients (110a-h); calculating (120) a first likelihood data set (124) comprising a likelihood of said bit having a given value for each bit position from the first set of filter coefficients. A second bit sequence (103) comprising the bit at a different position is then correlated with the filters to create a second set of filter coefficients (10a-h), from which a second likelihood data set (124) is calculated. A soft output bit (26) comprising a probability weighted bit value from data corresponding to the bit at a first and second bit positions from the first and second likelihood data sets respectively is then calculated.

Abstract: A method of processing a digitally encoded radio signal (102) comprising a bit to be determined is disclosed. The method comprises correlating a first bit sequence (103) comprising the bit with a plurality of predetermined filters (104a-h) to create a first set of filter coefficients (110a-h); calculating (120) a first likelihood data set (124) comprising a likelihood of said bit having a given value for each bit position from the first set of filter coefficients. A second bit sequence (103) comprising the bit at a different position is then correlated with the filters to create a second set of filter coefficients (10a-h), from which a second likelihood data set (124) is calculated. A soft output bit (26) comprising a probability weighted bit value from data corresponding to the bit at a first and second bit positions from the first and second likelihood data sets respectively is then calculated.