Patents by Inventor Eizo Mitani

Eizo Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6395588
    Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1˜1016 to 1˜1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: May 28, 2002
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Tsutomu Igarashi, Kenji Arimochi, Teruo Yokoyama, Eizo Mitani, Shigeru Kuroda, Junichiro Nikaido, Yasunori Tateno
  • Publication number: 20020008248
    Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1×1016 to 1×1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.
    Type: Application
    Filed: June 15, 2001
    Publication date: January 24, 2002
    Applicant: Fujitsu Quantum Devices Limited
    Inventors: Tsutomu Igarashi, Kenji Arimochi, Teruo Yokoyama, Eizo Mitani, Shigeru Kuroda, Junichiro Nikaido, Yasunori Tateno
  • Patent number: 6278141
    Abstract: An enhancement-mode semiconductor device includes a barrier layer formed on a channel layer and a gate electrode provided on the barrier layer, wherein the gate electrode is formed with an orientation chosen so as to maximize a threshold voltage of the semiconductor device.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Eizo Mitani, Hiroyuki Oguri
  • Patent number: 6274893
    Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1×1016 to 1×1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: August 14, 2001
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Tsutomu Igarashi, Kenji Arimochi, Teruo Yokoyama, Eizo Mitani, Shigeru Kuroda, Junichiro Nikaido, Yasunori Tateno