Patents by Inventor Ekgachai Kenganantanon
Ekgachai Kenganantanon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887864Abstract: Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.Type: GrantFiled: May 21, 2021Date of Patent: January 30, 2024Assignee: Microchip Technology IncorporatedInventors: Wichai Kovitsophon, Rangsun Kitnarong, Ekgachai Kenganantanon, Pattarapon Poolsup, Watcharapong Nokde, Chanyuth Junjuewong
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Publication number: 20220344173Abstract: Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.Type: ApplicationFiled: May 21, 2021Publication date: October 27, 2022Applicant: Microchip Technology IncorporatedInventors: Wichai Kovitsophon, Rangsun Kitnarong, Ekgachai Kenganantanon, Pattarapon Poolsup, Watcharapong Nokde, Chanyuth Junjuewong
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Patent number: 11145574Abstract: Semiconductor device packages may include a die-attach pad and a semiconductor die supported above the die-attach pad. A spacer comprising an electrically conductive material may be supported above the semiconductor die or between the semiconductor die and the die-attach pad. A wire bond may extend from a bond pad on an active surface of the semiconductor die to the spacer. Another wire bond may extend from the spacer to a lead finger or the die-attach pad. An encapsulant material may encapsulate the semiconductor die, the spacer, the wire bond, the other wire bond, the die-attach pad, and a portion of any lead fingers.Type: GrantFiled: December 28, 2018Date of Patent: October 12, 2021Assignee: Microchip Technology IncorporatedInventors: Oliver Mabutas, Ekgachai Kenganantanon, Wichai Kovitsophon, Tarapong Soontornvipart, Peerapat Bunkhem
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Publication number: 20200135620Abstract: Semiconductor device packages may include a die-attach pad and a semiconductor die supported above the die-attach pad. A spacer comprising an electrically conductive material may be supported above the semiconductor die or between the semiconductor die and the die-attach pad. A wire bond may extend from a bond pad on an active surface of the semiconductor die to the spacer. Another wire bond may extend from the spacer to a lead finger or the die-attach pad. An encapsulant material may encapsulate the semiconductor die, the spacer, the wire bond, the other wire bond, the die-attach pad, and a portion of any lead fingers.Type: ApplicationFiled: December 28, 2018Publication date: April 30, 2020Inventors: Oliver Mabutas, Ekgachai Kenganantanon, Wichai Kovitsophon, Tarapong Soontornvipart, Peerapat Bunkhem
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Publication number: 20190221502Abstract: An apparatus includes a lead frame paddle configured for mounting a semiconductor die. The apparatus further includes a plating area formed on the lead frame paddle. The plating area is configured to receive a down bond from a semiconductor die placed on the lead frame paddle. The apparatus further includes an exposed gap between an outer edge of the plating area and an outer edge of the lead frame paddle.Type: ApplicationFiled: March 29, 2018Publication date: July 18, 2019Applicant: Microchip Technology IncorporatedInventors: Joseph Fernandez, Rangsun Kitnarong, Tarapong Soontornvipart, Janwit Apirukaramwong, Prachit Punyapor, Supakrits Suttiwat, Ekgachai Kenganantanon
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Publication number: 20170005030Abstract: According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple.Type: ApplicationFiled: September 12, 2016Publication date: January 5, 2017Applicant: Microchip Technology IncorporatedInventors: Rangsun Kitnarong, Prachit Punyapor, Ekgachai Kenganantanon
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Publication number: 20160148876Abstract: According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple.Type: ApplicationFiled: November 19, 2015Publication date: May 26, 2016Applicant: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Rangsun Kitnarong, Prachit Punyapor, Ekgachai Kenganantanon
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Patent number: 9263397Abstract: A method for providing alignment in a die picking process may include aligning a semiconductor wafer based on a reference die, forming an indicator line relative to the reference die by picking a number of dice along a line extending across the wafer, and using the reference line to monitor a position of the picking machine relative to the wafer. A die attach machine may include a control system for automatically implementing such method.Type: GrantFiled: March 5, 2014Date of Patent: February 16, 2016Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Matthew Gibson, Prem Na-Namchiew, Ekgachai Kenganantanon, Mathew Bunker
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Publication number: 20150187688Abstract: A method for manufacturing an integrated circuit device is disclosed. A leadframe is provided having a die support area configured to receive an integrated circuit die and a plurality of leadframe fingers adjacent the die support area, each leadframe finger including a finger tip area at one end of the leadframe finger. The leadframe is masked such that one or more areas of the leadframe are covered and one or more areas of the leadframe are exposed, wherein for each leadframe finger, a first region of the respective finger tip area is covered by the masking and a second region of the respective finger tip area is exposed. The one or more exposed areas of the leadframe are silver plated such for each leadframe finger, the second region of the respective finger tip area is sliver plated and the first region of the respective finger tip area is not sliver plated.Type: ApplicationFiled: December 23, 2014Publication date: July 2, 2015Inventors: Joseph D. Fernandez, Tarapong Soontornvipart, Ekgachai Kenganantanon, Oliver Mabutas, Greg Perzanowski
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Publication number: 20140264962Abstract: A method for providing alignment in a die picking process may include aligning a semiconductor wafer based on a reference die, forming an indicator line relative to the reference die by picking a number of dice along a line extending across the wafer, and using the reference line to monitor a position of the picking machine relative to the wafer. A die attach machine may include a control system for automatically implementing such method.Type: ApplicationFiled: March 5, 2014Publication date: September 18, 2014Inventors: Matthew Gibson, Prem Na-Namchiew, Ekgachai Kenganantanon, Mathew Bunker
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Publication number: 20140235033Abstract: A silicon wafer saw can be set to either three or four different cutting angle orientations from a zero degree reference to produce integrated circuit dice having corners greater than 90 degrees. Three different saw angle orientations will produce six sided dice, and four different saw cutting angle orientations will produce eight sided dice.Type: ApplicationFiled: February 18, 2013Publication date: August 21, 2014Applicant: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Matthew Bunker, Ekgachai Kenganantanon, Surapol Sawatjeen
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Patent number: 7927921Abstract: A uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice. A non-conductive adhesive is dispensed onto mating faces of die attach paddles of leadframes. The dice are placed into the non-conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof.Type: GrantFiled: May 27, 2009Date of Patent: April 19, 2011Assignee: Microchip Technology IncorporatedInventors: Ekgachai Kenganantanon, Surapol Sawatjeen
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Publication number: 20100304532Abstract: A uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice. A non-conductive adhesive is dispensed onto mating faces of die attach paddles of leadframes. The dice are placed into the non-conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof.Type: ApplicationFiled: May 27, 2009Publication date: December 2, 2010Inventors: Ekgachai Kenganantanon, Surapol Sawatjeen