Patents by Inventor Ekgachai Kenganantanon

Ekgachai Kenganantanon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887864
    Abstract: Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 30, 2024
    Assignee: Microchip Technology Incorporated
    Inventors: Wichai Kovitsophon, Rangsun Kitnarong, Ekgachai Kenganantanon, Pattarapon Poolsup, Watcharapong Nokde, Chanyuth Junjuewong
  • Publication number: 20220344173
    Abstract: Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.
    Type: Application
    Filed: May 21, 2021
    Publication date: October 27, 2022
    Applicant: Microchip Technology Incorporated
    Inventors: Wichai Kovitsophon, Rangsun Kitnarong, Ekgachai Kenganantanon, Pattarapon Poolsup, Watcharapong Nokde, Chanyuth Junjuewong
  • Patent number: 11145574
    Abstract: Semiconductor device packages may include a die-attach pad and a semiconductor die supported above the die-attach pad. A spacer comprising an electrically conductive material may be supported above the semiconductor die or between the semiconductor die and the die-attach pad. A wire bond may extend from a bond pad on an active surface of the semiconductor die to the spacer. Another wire bond may extend from the spacer to a lead finger or the die-attach pad. An encapsulant material may encapsulate the semiconductor die, the spacer, the wire bond, the other wire bond, the die-attach pad, and a portion of any lead fingers.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 12, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Oliver Mabutas, Ekgachai Kenganantanon, Wichai Kovitsophon, Tarapong Soontornvipart, Peerapat Bunkhem
  • Publication number: 20200135620
    Abstract: Semiconductor device packages may include a die-attach pad and a semiconductor die supported above the die-attach pad. A spacer comprising an electrically conductive material may be supported above the semiconductor die or between the semiconductor die and the die-attach pad. A wire bond may extend from a bond pad on an active surface of the semiconductor die to the spacer. Another wire bond may extend from the spacer to a lead finger or the die-attach pad. An encapsulant material may encapsulate the semiconductor die, the spacer, the wire bond, the other wire bond, the die-attach pad, and a portion of any lead fingers.
    Type: Application
    Filed: December 28, 2018
    Publication date: April 30, 2020
    Inventors: Oliver Mabutas, Ekgachai Kenganantanon, Wichai Kovitsophon, Tarapong Soontornvipart, Peerapat Bunkhem
  • Publication number: 20190221502
    Abstract: An apparatus includes a lead frame paddle configured for mounting a semiconductor die. The apparatus further includes a plating area formed on the lead frame paddle. The plating area is configured to receive a down bond from a semiconductor die placed on the lead frame paddle. The apparatus further includes an exposed gap between an outer edge of the plating area and an outer edge of the lead frame paddle.
    Type: Application
    Filed: March 29, 2018
    Publication date: July 18, 2019
    Applicant: Microchip Technology Incorporated
    Inventors: Joseph Fernandez, Rangsun Kitnarong, Tarapong Soontornvipart, Janwit Apirukaramwong, Prachit Punyapor, Supakrits Suttiwat, Ekgachai Kenganantanon
  • Publication number: 20170005030
    Abstract: According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple.
    Type: Application
    Filed: September 12, 2016
    Publication date: January 5, 2017
    Applicant: Microchip Technology Incorporated
    Inventors: Rangsun Kitnarong, Prachit Punyapor, Ekgachai Kenganantanon
  • Publication number: 20160148876
    Abstract: According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple.
    Type: Application
    Filed: November 19, 2015
    Publication date: May 26, 2016
    Applicant: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Rangsun Kitnarong, Prachit Punyapor, Ekgachai Kenganantanon
  • Patent number: 9263397
    Abstract: A method for providing alignment in a die picking process may include aligning a semiconductor wafer based on a reference die, forming an indicator line relative to the reference die by picking a number of dice along a line extending across the wafer, and using the reference line to monitor a position of the picking machine relative to the wafer. A die attach machine may include a control system for automatically implementing such method.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: February 16, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Matthew Gibson, Prem Na-Namchiew, Ekgachai Kenganantanon, Mathew Bunker
  • Publication number: 20150187688
    Abstract: A method for manufacturing an integrated circuit device is disclosed. A leadframe is provided having a die support area configured to receive an integrated circuit die and a plurality of leadframe fingers adjacent the die support area, each leadframe finger including a finger tip area at one end of the leadframe finger. The leadframe is masked such that one or more areas of the leadframe are covered and one or more areas of the leadframe are exposed, wherein for each leadframe finger, a first region of the respective finger tip area is covered by the masking and a second region of the respective finger tip area is exposed. The one or more exposed areas of the leadframe are silver plated such for each leadframe finger, the second region of the respective finger tip area is sliver plated and the first region of the respective finger tip area is not sliver plated.
    Type: Application
    Filed: December 23, 2014
    Publication date: July 2, 2015
    Inventors: Joseph D. Fernandez, Tarapong Soontornvipart, Ekgachai Kenganantanon, Oliver Mabutas, Greg Perzanowski
  • Publication number: 20140264962
    Abstract: A method for providing alignment in a die picking process may include aligning a semiconductor wafer based on a reference die, forming an indicator line relative to the reference die by picking a number of dice along a line extending across the wafer, and using the reference line to monitor a position of the picking machine relative to the wafer. A die attach machine may include a control system for automatically implementing such method.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 18, 2014
    Inventors: Matthew Gibson, Prem Na-Namchiew, Ekgachai Kenganantanon, Mathew Bunker
  • Publication number: 20140235033
    Abstract: A silicon wafer saw can be set to either three or four different cutting angle orientations from a zero degree reference to produce integrated circuit dice having corners greater than 90 degrees. Three different saw angle orientations will produce six sided dice, and four different saw cutting angle orientations will produce eight sided dice.
    Type: Application
    Filed: February 18, 2013
    Publication date: August 21, 2014
    Applicant: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Matthew Bunker, Ekgachai Kenganantanon, Surapol Sawatjeen
  • Patent number: 7927921
    Abstract: A uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice. A non-conductive adhesive is dispensed onto mating faces of die attach paddles of leadframes. The dice are placed into the non-conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: April 19, 2011
    Assignee: Microchip Technology Incorporated
    Inventors: Ekgachai Kenganantanon, Surapol Sawatjeen
  • Publication number: 20100304532
    Abstract: A uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice. A non-conductive adhesive is dispensed onto mating faces of die attach paddles of leadframes. The dice are placed into the non-conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof.
    Type: Application
    Filed: May 27, 2009
    Publication date: December 2, 2010
    Inventors: Ekgachai Kenganantanon, Surapol Sawatjeen