Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.

Abstract: Methods, systems, and devices for temperature-dependent refresh operations are described. A memory system may adjust refresh operations based on a temperature of the memory system to reduce a refresh current and improve reliability of the refresh operations. For example, the memory system may include a temperature sensor configured to provide temperature information associated with a memory device. Based on the temperature information, the memory system may, in response to a refresh command, activate a set of access lines (e.g., word lines) to refresh memory cells coupled with the access lines, where a count of the set of access lines (e.g., how many access lines are included in the set) may be based on the temperature information. In some examples, the count of the set may be determined based on comparing the temperature information to one or more temperature thresholds.

Abstract: Electronic devices for correcting a duty-cycle of a clock signal are disclosed. An electronic device may include circuitry configured to receive an input clock signal and generate, based on the input clock signal, a number of corrected clock signals. The circuitry may further be configured to generate, via an amplifier of the circuitry, a number of error signals based on the number of corrected clock signals and adjust a duty cycle of the number of corrected clock signals based on the number of error signals. Further, the circuitry may be configured to disable the amplifier in response to determining that the input clock signal is disabled. Associated apparatuses and methods are also disclosed.

Abstract: Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes a duty-cycle adjuster, a circuit, and a clock detector. The duty-cycle adjuster is configured to receive an input clock signal and correct a duty-cycle of a corrected clock signal relative to an input duty-cycle of the input clock signal. The circuit is configured to control corrections made to the duty-cycle of the corrected clock signal by the duty-cycle adjuster. The clock detector is configured to disable the corrections made to the duty-cycle of the corrected clock signal responsive to a detection that the input clock signal is disabled.

Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.

Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.

Abstract: Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes a duty-cycle adjuster, a circuit, and a clock detector. The duty-cycle adjuster is configured to receive an input clock signal and correct a duty-cycle of a corrected clock signal relative to an input duty-cycle of the input clock signal. The circuit is configured to control corrections made to the duty-cycle of the corrected clock signal by the duty-cycle adjuster. The clock detector is configured to disable the corrections made to the duty-cycle of the corrected clock signal responsive to a detection that the input clock signal is disabled.

Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.

Abstract: Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes an integrator circuit, an amplifier circuit, and an electrically controllable switch. The integrator circuit is configured to provide an integrator signal indicating substantially an integral of a corrected clock signal. The amplifier circuit is configured to be disabled responsive to a detection that an input clock signal is disabled. The amplifier circuit includes a first amplifier input terminal and a second amplifier input terminal. The electrically controllable switch is configured to selectively electrically connect the first amplifier input terminal to the second amplifier input terminal responsive to the detection that the input clock signal is disabled. A method of correcting a duty-cycle of an input clock signal includes adjusting a corrected duty-cycle of the corrected clock signal responsive to a first error signal and a second error signal from the amplifier circuit.

Abstract: Methods, systems, and devices for back-bias optimization are described. An apparatus, such as an electronic apparatus, may include a first substrate region and a second substrate region. The apparatus may also include a voltage generator that is disposed on the first substrate region and that includes an output terminal coupled with a conductive path. The apparatus may also include a set of clamp circuits disposed on the second substrate region. The set of clamp circuits may be configured selectively couple the conductive path with a voltage supply.