Patents by Inventor Eli Kupermann
Eli Kupermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10677618Abstract: Embodiments of the present disclosure provide techniques for sensor testing for computing devices during initial movement of the device, such as movement on a manufacturing line. In one instance, a device with integral sensor testing during initial movement of the device may include a plurality of sensors and a sensor test block coupled with the plurality of sensors, to detect, collect and/or report readings provided by at least some of the sensors in response to movement of the device between at least a first test station and a second test station. Other embodiments may be described and/or claimed.Type: GrantFiled: March 4, 2016Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Yael Yanai, Yehiel Shilo, Eli Kupermann, Chen-Hsun Wu, Elena Agranovsky, Marlon D. Bada
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Patent number: 10229086Abstract: Technologies for controlling timing calibration of a dedicated inter-integrated circuit data bus by a primary microcontroller are disclosed. The primary microcontroller performs a data transfer with a secondary integrated circuit using the dedicated inter-integrated circuit data bus, and determines a duration of the data transfer. If the duration is outside of an acceptable range, the primary microcontroller updates one or more data transfer timing parameters so that the duration of future data transfers are closer to the acceptable range.Type: GrantFiled: December 26, 2015Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Yuli Barcohen, Eli Kupermann, Alexander Brill
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Patent number: 9836113Abstract: In an embodiment, a processor includes first logic to determine first power to be provided to a first portion of a computational resource during a time period. The first portion may be reserved for execution by the processor of a first workload to be executed during the time period. The first power may be determined based at least in part on the first workload and independently of a second workload. The processor may include second logic to determine second power to be provided to a second portion of the computational resource during the time period. The second portion may be reserved for execution by the processor of the second workload during the time period. The second power may be determined based at least in part on the second workload and independently of the first workload.Type: GrantFiled: December 23, 2013Date of Patent: December 5, 2017Assignee: Intel CorporationInventors: Eli Kupermann, Rajasekaran Andiappan, Suryaprasad Kareenahalli, Yuli Barcohen
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Patent number: 9820018Abstract: Described is an apparatus comprising: a processor operable to execute a virtual machine manager (VMM) which is to manage a virtual machine (VM) for a hardware intellectual property (IP) block; a communication fabric; and a hardware IP block coupled to the processor via the communication fabric, wherein the hardware IP block is to be coupled to a first set of one or more sensors, and wherein the VM and the hardware IP block are operable to process data collected from the first set.Type: GrantFiled: December 12, 2015Date of Patent: November 14, 2017Assignee: Intel CorporationInventors: Eli Kupermann, Suryaprasad Kareenahalli, Christian Soby, Amit Kimelman, Rajasekaran Andiappan, Elena Agranovsky
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Publication number: 20170254683Abstract: Embodiments of the present disclosure provide techniques for sensor testing for computing devices during initial movement of the device, such as movement on a manufacturing line. In one instance, a device with integral sensor testing during initial movement of the device may include a plurality of sensors and a sensor test block coupled with the plurality of sensors, to detect, collect and/or report readings provided by at least some of the sensors in response to movement of the device between at least a first test station and a second test station. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 4, 2016Publication date: September 7, 2017Inventors: Yael Yanai, Yehiel Shilo, Eli Kupermann, Chen-Hsun Wu, Elena Agranovsky, Marlon D. Bada
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Publication number: 20170185560Abstract: Technologies for controlling timing calibration of a dedicated inter-integrated circuit data bus by a primary microcontroller are disclosed. The primary microcontroller performs a data transfer with a secondary integrated circuit using the dedicated inter-integrated circuit data bus, and determines a duration of the data transfer. If the duration is outside of an acceptable range, the primary microcontroller updates one or more data transfer timing parameters so that the duration of future data transfers are closer to the acceptable range.Type: ApplicationFiled: December 26, 2015Publication date: June 29, 2017Inventors: Yuli Barcohen, Eli Kupermann, Alexander Brill
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Patent number: 9684360Abstract: In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed.Type: GrantFiled: October 30, 2014Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Eli Kupermann, Elena Agranovsky
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Publication number: 20170171645Abstract: Described is an apparatus comprising: a processor operable to execute a virtual machine manager (VMM) which is to manage a virtual machine (VM) for a hardware intellectual property (IP) block; a communication fabric; and a hardware IP block coupled to the processor via the communication fabric, wherein the hardware IP block is to be coupled to a first set of one or more sensors, and wherein the VM and the hardware IP block are operable to process data collected from the first set.Type: ApplicationFiled: December 12, 2015Publication date: June 15, 2017Inventors: Eli Kupermann, Suryaprasad Kareenahalli, Christian Soby, Amit Kimelman, Rajasekaran Andiappan, Elena Agranovsky
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Patent number: 9619671Abstract: A platform including a security system is described. The security system comprises, in one embodiment, a multi-state system having a plurality of modes, available whenever the platform has a source of power. The modes comprise an unarmed mode, in which the security system is not protecting the platform, an armed mode, in which the platform is protected, the armed mode reached from the unarmed mode, after an arming command, and a suspecting mode, in which the platform is suspecting theft, the suspecting mode reached from the armed mode, when a risk behavior is detected.Type: GrantFiled: December 22, 2011Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Michael Berger, Mukesh Kataria, Jeffrey M. Tripp, Yasser Rasheed, David Birnbaum, Hung P. Huynh, Eli Kupermann, Mazen G. Gedeon, Joshua M. Resch
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Publication number: 20160124490Abstract: In one embodiment, a processor comprises: at least one core to execute instructions; a memory coupled to the at least one core, the memory including a plurality of pages to store information; and a page manager coupled to the memory, the page manager to access metadata of a page table entry associated with a page of the memory and update usage information of an entry of a database, the entry of the database associated with the page of the memory. The page manager may cause at least a portion of the memory to be dynamically powered down based at least in part on the usage information. Other embodiments are described and claimed.Type: ApplicationFiled: October 30, 2014Publication date: May 5, 2016Inventors: Eli Kupermann, Elena Agranovsky
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Publication number: 20150370564Abstract: Described is an integrated circuit (IC) comprising: a processor; and a plurality of registers coupled to the processor, wherein the processor to select one of the registers of the plurality to stall execution of an instruction by a predetermined time.Type: ApplicationFiled: June 24, 2014Publication date: December 24, 2015Inventors: Eli Kupermann, Yuli Barcohen, Suryaprasad Kareenahalli
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Patent number: 9141946Abstract: Systems and methods may provide for implementing a dynamic payment service. In one example, the method may generate a request communication including purchase detail information relating to an item to request credit from a vendor to conduct a transaction relating to the item, determine a scope of credit to be issued to conduct the transaction relating to the item based on the purchase detail information, and generate a payment communication including the transaction information to complete the transaction relating to the item.Type: GrantFiled: April 17, 2012Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Eli Kupermann, Jasmeet Chhabra, Irena Riji, Sanjay Bakshi
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Publication number: 20150177820Abstract: In an embodiment, a processor includes first logic to determine first power to be provided to a first portion of a computational resource during a time period. The first portion may be reserved for execution by the processor of a first workload to be executed during the time period. The first power may be determined based at least in part on the first workload and independently of a second workload. The processor may include second logic to determine second power to be provided to a second portion of the computational resource during the time period. The second portion may be reserved for execution by the processor of the second workload during the time period. The second power may be determined based at least in part on the second workload and independently of the first workload.Type: ApplicationFiled: December 23, 2013Publication date: June 25, 2015Inventors: Eli Kupermann, Rajasekaran Andiappan, Suryaprasad Kareenahalli, Yuli Barcohen
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Publication number: 20140201030Abstract: Systems and methods may provide for implementing a dynamic payment service. In one example, the method may generate a request communication including purchase detail information relating to an item to request credit from a vendor to conduct a transaction relating to the item, determine a scope of credit to be issued to conduct the transaction relating to the item based on the purchase detail information, and generate a payment communication including the transaction information to complete the transaction relating to the item.Type: ApplicationFiled: April 17, 2012Publication date: July 17, 2014Inventors: Eli Kupermann, Jasmeet Chhabra, Irena Riji, Sanjay Bakshi
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Patent number: 8701183Abstract: A method, system, and computer program product containing instructions to provide hardware-based human presence detection. Rather than rely upon software to display a CAPTCHA image, hardware in the form of a sprite engine of a graphics device is used to write a random text string directly to the display device, overlaying the user interface provided by software. Because the sprite engine is isolated from a host operating system for the system, the random text string cannot be captured and processed by software robots running under the host operating system.Type: GrantFiled: September 30, 2010Date of Patent: April 15, 2014Assignee: Intel CorporationInventors: Avraham Mualem, Eli Kupermann
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Publication number: 20140020121Abstract: A platform including a security system is described. The security system comprises, in one embodiment, a multi-state system having a plurality of modes, available whenever the platform has a source of power. The modes comprise an unarmed mode, in which the security system is not protecting the platform, an armed mode, in which the platform is protected, the armed mode reached from the unarmed mode, after an arming command, and a suspecting mode, in which the platform is suspecting theft, the suspecting mode reached from the armed mode, when a risk behavior is detected.Type: ApplicationFiled: December 22, 2011Publication date: January 16, 2014Inventors: Michael Berger, Mukesh Kataria, Jeffrey M. Tripp, Yasser Rasheed, David Birnbaum, Hung P. Huynh, Eli Kupermann, Mazen G. Gedeon, Joshua M. Resch
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Publication number: 20120084854Abstract: A method, system, and computer program product containing instructions to provide hardware-based human presence detection. Rather than rely upon software to display a CAPTCHA image, hardware in the form of a sprite engine of a graphics device is used to write a random text string directly to the display device, overlaying the user interface provided by software. Because the sprite engine is isolated from a host operating system for the system, the random text string cannot be captured and processed by software robots running under the host operating system.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Inventors: Avraham Mualem, Eli Kupermann
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Patent number: 7900072Abstract: Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.Type: GrantFiled: December 21, 2007Date of Patent: March 1, 2011Assignee: Intel CorporationInventors: Michael Berger, Michael Derr, Joshua Resch, Mukesh Kataria, Mazen Gedeon, Eli Kupermann, Jeffrey John Vick
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Publication number: 20100082955Abstract: In general, in one aspect, the disclosure describes an apparatus that includes updatable non-volatile memory to store firmware and non-updateable non-volatile memory to store an interrupt sequence. The apparatus includes a chip interface to receive an interrupt instruction from management firmware. Receipt of the interrupt instruction controls access to and initiation of the interrupt sequence. After initiation of the interrupt sequence the apparatus may receive a firmware update and/or validate the firmware is from a valid source. The validation of the firmware may include utilizing the management firmware to verify the cryptographic signature for the firmware.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Jasmeet Chhabra, Mazen Gedeon, Sanjay Bakshi, Eli Kupermann
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Publication number: 20090164819Abstract: Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Inventors: Michael Berger, Michael N. Derr, Joshua Resch, Mukesh Kataria, Mazen Gedeon, Eli Kupermann, Jeffrey John Vick