Abstract: An electronic package for use with a printed circuit board is provided. The electronic package includes a ground layer having an upper and lower section, a semiconductor chip, a conductive signal layer and a ground plane having a first section electrically connected to the upper section of the ground layer and a second section substantially planar with said lower section of said ground layer, the second section of the ground plane having an additional area to prevent cracking of a solder connection between the ground layer, the ground plane and the printed circuit board.

Abstract: A chip package having an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another. Such a staggered arrangement permits a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggered in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.

Abstract: A chip package having an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another. Such a staggered arrangement permits a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggering in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.