Abstract: A data processor (10) has a floating-point execution unit (32) for executing a floating-point compare operation using two data operands. The execution unit (32) uses mantissa comparator logic (107) to perform a bit-wise comparison of a mantissa portion of a first operand with the mantissa portion of a second operand, and to provide a mantissa comparison result. Similarly, exponent comparator logic (122) performs a bit-wise comparison of an exponent portion of the first operand with the exponent portion of the second, and provides an exponent comparison result. Comparator logic (114) in the execution unit receives the mantissa comparison result and the exponent comparison result. If the exponent portions of the two operands are not equal, the comparator logic (114) uses an operand sign bit of each operand and the exponent comparison result to order the two operands.

Abstract: A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tapped output of the delay line goes through a two phase generator which in turn feeds back to the PD for comparison with the reference clock. This process is repeated until phase locking is obtained.

Abstract: A replacement method is provided for improving the hit rate and testability of a page address translation cache (PATC). The replacement scheme uses a modified FIFO replacement algorithm. A circular shift register has a pointer which points to each of a predetermined number of translation descriptors stored in the PATC. The shift register pointer has an input for receiving the logic state of a valid bit associated with each of the translation descriptors stored in the PATC. The shift register is advanced after every translation cycle, until the logic state of the valid bit indicates that the denoted translation descriptor is invalid, or until a read/write control signal indicates a PATC write is in progress. Upon detecting an invalid translation descriptor, the circular shift register is disabled, and remains disabled until an address translation "miss" occurs, and a replacement entry is loaded into the PATC. If, however, an address translation miss occurs while the circular shift register is enabled (i.e.